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Support incremental builds for the bitstream.
By patching the UDS and UDI into an already built bitstream, it is now not necessary to rebuild the entire build flow when changing the UDS and the UDI. This lowers re-build times significantly. Signed-off-by: Joachim Strömbergson <[email protected]>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,35 @@ | ||
| //====================================================================== | ||
| // | ||
| // udi_rom.v | ||
| // --------- | ||
| // UDI rom generated by instatiating named SB_LUT4 resources. | ||
| // Note: This makes the design tech specicific. | ||
| // | ||
| // | ||
| // Author: Claire Xiena Wolf. | ||
| // Copyright (C) 2023 - Tillitis AB | ||
| // SPDX-License-Identifier: GPL-2.0-only | ||
| // | ||
| //====================================================================== | ||
|
|
||
| module udi_rom ( | ||
| input wire [0:0] addr, | ||
| output wire [31:0] data | ||
| ); | ||
| generate | ||
| genvar ii; | ||
| for (ii = 0; ii < 32; ii = ii + 1'b1) begin: luts | ||
| (* udi_rom_idx=ii, keep *) SB_LUT4 | ||
| #( | ||
| .LUT_INIT({2'h1}) | ||
| ) lut_i ( | ||
| .I0(addr[0]), | ||
| .O(data[ii]) | ||
| ); | ||
| end | ||
| endgenerate | ||
| endmodule | ||
|
|
||
| //====================================================================== | ||
| // EOF udi_rom.v | ||
| //====================================================================== |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,39 @@ | ||
| //====================================================================== | ||
| // | ||
| // uds_rom.v | ||
| // --------- | ||
| // UDS rom. Generated by instantiating named SB_LUT4 resources. | ||
| // Note: This makes the design technology specific. | ||
| // | ||
| // | ||
| // Author: Claire Xenia Wolf | ||
| // Copyright (C) 2023 - YosysHQ, Tillitis AB | ||
| // SPDX-License-Identifier: GPL-2.0-only | ||
| // | ||
| //====================================================================== | ||
|
|
||
| `default_nettype none | ||
|
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||
| module uds_rom( | ||
| input wire [2:0] addr, | ||
| input wire re, | ||
| output wire [31:0] data | ||
| ); | ||
|
|
||
| generate | ||
| genvar ii; | ||
| for (ii = 0; ii < 32; ii = ii + 1'b1) begin: luts | ||
| (* uds_rom_idx=ii, keep *) SB_LUT4 | ||
| #( | ||
| .LUT_INIT({8'ha6 ^ ii[7:0], 8'h00}) | ||
| ) lut_i ( | ||
| .I0(addr[0]), .I1(addr[1]), .I2(addr[2]), .I3(re), | ||
| .O(data[ii]) | ||
| ); | ||
| end | ||
| endgenerate | ||
| endmodule // uds_rom | ||
|
|
||
| //====================================================================== | ||
| // EOF uds_rom.v | ||
| //====================================================================== |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,63 @@ | ||
| # -*- coding: utf-8 -*- | ||
| #======================================================================= | ||
| # | ||
| # personalize.py | ||
| # -------------- | ||
| # Python program that patches the UDS and UDI implemented using | ||
| # named LUT4 instances to have unique initial values, not the generic | ||
| # values used during synthesis, p&r and mapping. This allows us to | ||
| # generate device unique bitstreams without running the complete flow. | ||
| # | ||
| # | ||
| # Copyright (C) 2023 Tillitis AB | ||
| # Written by Myrtle Shah <[email protected]> | ||
| # SPDX-License-Identifier: GPL-2.0-only | ||
| # | ||
| #======================================================================= | ||
|
|
||
| import os | ||
|
|
||
| def parse_hex(file, length): | ||
| data = [] | ||
| with open(file, "r") as f: | ||
| for line in f: | ||
| l = line.strip() | ||
| if len(l) > 0: | ||
| data.append(int(l, 16)) | ||
| assert len(data) == length, len(data) | ||
| return data | ||
|
|
||
| def rewrite_lut(lut, idx, data, has_re=False): | ||
| # each LUT provides one bit per 32-bit word out of 64/256 bits total | ||
| new_init = 0 | ||
| for i, word in enumerate(data): | ||
| if (word >> idx) & 0x1: | ||
| # repeat so inputs above address have a don't care value | ||
| repeat = (16 // len(data)) | ||
| for k in range(repeat): | ||
| # UDS also has a read enable | ||
| # LUT output is zero if this isn't asserted | ||
| if has_re and k < (repeat // 2): | ||
| continue | ||
| new_init |= (1 << (k * len(data) + i)) | ||
| lut.setParam("LUT_INIT", f"{new_init:016b}") | ||
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| uds = parse_hex(os.environ["UDS_HEX"], 8) | ||
| udi = parse_hex(os.environ["UDI_HEX"], 2) | ||
|
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| uds_lut_count = 0 | ||
| udi_lut_count = 0 | ||
|
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| for cell_name, cell in ctx.cells: | ||
| if "uds_rom_idx" in cell.attrs: | ||
| index = int(cell.attrs["uds_rom_idx"], 2) | ||
| rewrite_lut(cell, index, uds, True) | ||
| uds_lut_count += 1 | ||
| if "udi_rom_idx" in cell.attrs: | ||
| index = int(cell.attrs["udi_rom_idx"], 2) | ||
| rewrite_lut(cell, index, udi, False) | ||
| udi_lut_count += 1 | ||
| assert uds_lut_count == 32, uds_lut_count | ||
| assert udi_lut_count == 32, udi_lut_count | ||
|
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| write_bitstream(ctx, os.environ["OUT_ASC"]) |