mpfs_opensbi: Re-organize SBI areas so that RW areas follow each other #185

pussuw · 2023-11-27T13:39:32Z

Change the ordering of the SBI areas so that:

The first area is the executable area (.text)
The second area is the heap (RW)
The last area is the scratch registers (RW)

This makes it easier to encode PMP areas for OpenSBI.

- boots from eNVM - uses lim memory for RAM - has console on uart 0 - has procfs enabled - has most of nsh commands enabled Signed-off-by: Jukka Laitinen <[email protected]>

- Change git repository urls to point to our tiiuae repos for nuttx & nuttx apps - Remove most of the the build steps, leave just arm-12 and riscv; arm-12 has a build for stm32f7, and riscv for mpfs Signed-off-by: Jukka Laitinen <[email protected]>

…ptimized version in tiiuae repo Signed-off-by: Jukka Laitinen <[email protected]>

…iver to re-initialize on rx timeout If the interface is UP, and no packets are received in 30s, re-initialize the interface by calling the already implemented mpfs_txtimeout_expiry. This is a temporary workaround for a bug where IF might be UP and working but packets can only be transmitted. Receive side just doesn't work at all. The original bug can be re-produced easily by disconnecting and reconnecting the ethernet cable while the IF is up. Signed-off-by: Jukka Laitinen <[email protected]>

SD-card clock speed is just forced to 50MHz. Note that to be correct, one should first set the SD-card into high-speed mode, but currently NuttX doesn't support this. With our cards, just setting the interface to 50MHz seems to work fine, and it removes the issue with 25MHZ clock causing disturbance on GPS bands. Typically cards which support high-speed mode just work with 50MHz interface clock. This patch should be reverted when the NuttX supports high-speed mode, and we can properly set it. Signed-off-by: Jukka Laitinen <[email protected]>

Signed-off-by: Jukka Laitinen <[email protected]>

…ootloader This removes the need to have all the DDR/clock configuration related "LIBERODEFS" flags defined, when not building a standalone/coldboot configuration All of this code is unused when not building with CONFIG_MPFS_BOOTLOADER Signed-off-by: Jukka Laitinen <[email protected]>

This is not the correct way to do this, but it gives a nice perf. boost

Disable macOS builds for now.

All other commands are disabled in send_recv(). Signed-off-by: Jani Paalijarvi <[email protected]>

Signed-off-by: Jani Paalijarvi <[email protected]>

…ef and forward declare devif_loopback Signed-off-by: Jukka Laitinen <[email protected]>

Signed-off-by: Jukka Laitinen <[email protected]>

… that takes care of the need for loopback

Remove unnecessary VQID shifting (16 -> 0). Give an error if RPTUN init fails.

Enable LINUX_ON_HART4 in rpmsg-ch2 defconfig of ICICLE board. Remove LINUX_ON_HART4 config from rpmsg-ch1 defconfig of ICICLE board.

Fix build warning when CONFIG_STM32F7_AUTONEG is not set Signed-off-by: Jukka Laitinen <[email protected]>

…ved IO area in protected build Signed-off-by: Jukka Laitinen <[email protected]>

Signed-off-by: Jukka Laitinen <[email protected]>

Just a temporary patch, need to implement some kind of scalable solution for this. It might be a good idea to map something else for the user to avoid using ecall to enter the kernel for simple reads ? Also, increase the L3 table size

Fix case where NULL is de-referenced via tx/rx buffer or descriptor. Only 1 queue is currently set up for each, so the indices 1,2,3 are not valid and should not be handled.

Instead of releasing rx descriptor twice and tx buffer twice.

Initially clear PMP for all harts, this fixes random warm reset issues. Signed-off-by: Ville Juven <[email protected]>

After read training, check also that the eye is centered properly. Sometimes after the training the width is long enough, but it is not centered. Signed-off-by: Jukka Laitinen <[email protected]>

Just verify that the delay for the selected clock != 0 Signed-off-by: Jukka Laitinen <[email protected]>

Corrections to CA training verify step. The original copied from HSS didn't make sense in all aspects: - The check is not per lane, so it should be out of the "for (lane_sel" loop. - The check wasn't proper. The expected outcome is just a vector of increasing numbers separated enough Signed-off-by: Jukka Laitinen <[email protected]>

PMPCFG_A_TOR region may have zero size. The pmp configuration currently fails for zero-sized TOR. This patch bypasses such a restriction. Also replace log2ceil with LOG2_CEIL from lib/math32.h. Signed-off-by: Eero Nurkkala <[email protected]>

These options are just wrong and a result of misunderstanding of the Polarfire SoC spec. There are no feature limitations in the CPU PMP implementation -> remove any configuration options added.

For TOR: Any size and 4-byte aligned address is required For NA4: Only size 4 and 4-byte aligned address is good For NAPOT: Minimum size is 8 bytes, minimum base alignment is 8 bytes, and size must be power-of-two aligned with base This commit simplifies these checks and removes all the nonsense added by a misunderstanding of how the MPFS / Polarfire SoC's PMP works.

The PMP setup should be done in the board specific code, at a much earlier stage. Granting all access is a security risk anyway.

Open PMP before the hart payload starts to execute

This adds option to do PMP configuration via mpfs_board_pmp_setup instead of just opening up everything. In this case, it is up to the specific board to implement the PMP configuration in whichever way it sees fit.

There is a problem when vfork() calls execv() (or execl()) to start a new application: When the parent thread calls vfork() it receives and gets the pid of the vforked task, and not the pid of the desired execv'ed application. see issue apache#3334 Signed-off-by: yangyalei <[email protected]>

Handle task spawn attributes as task spawn file actions are handled. Why? This removes the need for sched_lock() when the task is being spawned. When loading the new task from a file the scheduler can be locked for a VERY LONG time, in the order of hundreds of milliseconds! This is unacceptable for real time operation. Also fixes a latent bug in exec_module, spawn_file_actions is executed at a bad location; when CONFIG_ARCH_ADDRENV=y actions will point to the new process's address environment (as it is temporarily instantiated at that point). Fix this by moving it to after addrenv_restore.

…nsole off By setting "isconsole" to false, mpfs_serial stops outputting to console. This can be used to disable output to debug console in low level. Signed-off-by: Jukka Laitinen <[email protected]>

priv->msgid may grow past its boundaries, causing struct i2c_msg_s *msg = &priv->msgv[priv->msgid] to read data out of boundaris. Signed-off-by: Eero Nurkkala <[email protected]>

This adds support for detecting various tamper events. The interrupt handler makes noise at every detection. Perhaps easiest test is to attach JTAG debugger. TAMPER_TESTS -define has some nonexisting (not in repos) calls, perhaps could remove it alltogether. Signed-off-by: Eero Nurkkala <[email protected]>

Use only tests that will trigger a tamper event. Leave other tests outside. Signed-off-by: Eero Nurkkala <[email protected]>

pussuw · 2023-11-27T13:43:26Z

Not sure how this will fit to upstream, as the linker scripts differ a bit. Should be doable by something like:

    .text.sbi : {
      _ssbi_ddr = ABSOLUTE(.);
      sbi*
      riscv_atomic*
      riscv_locks*
      riscv_asm*
      _esbi_ddr = ABSOLUTE(.);
      . = ALIGN(0x2000);
      _sbi_heap_start = ABSOLUTE(.);
      . += 16k; /* OpenSBI heap, aligned, at least 16k */
      _sbi_heap_end = ABSOLUTE(.);
    } > ddr

    PROVIDE(_sbi_heap_size = _sbi_heap_end - _sbi_heap_start);

Change the ordering of the SBI areas so that: - The first area is the executable area (.text) - The second area is the heap (RW) - The last area is the scratch registers (RW) This makes it easier to encode PMP areas for OpenSBI.

pussuw · 2023-11-27T14:14:07Z

Looks like the arm target is broken in upstream as well

gpoulios

LGTM

jlaitine and others added 30 commits August 25, 2023 15:08

boards/riscv/mpfs/icicle/configs/standalone: Add a standalone target

c6ad5be

- boots from eNVM - uses lim memory for RAM - has console on uart 0 - has procfs enabled - has most of nsh commands enabled Signed-off-by: Jukka Laitinen <[email protected]>

arch/risc-v/src/opensbi/Make.defs: Switch opensbi to the nuttx/size o…

477df1a

…ptimized version in tiiuae repo Signed-off-by: Jukka Laitinen <[email protected]>

opensbi: Take SBI version that removes console into use

c03e56b

Fix standalone defconfig for CI

f10e650

Signed-off-by: Jukka Laitinen <[email protected]>

arch/risc-v/src/mpfs: Add mpfs canfd socket can driver

dd3fe0b

boards/risc-v/mpfs/icicle: add new target for testing mpfs canfd driver

b4414cb

mpfs/emmcsd: Set same base clock for SDR/DDR modes

75cbc77

mpfs/emmcsd: [HACK] Set 8-bit data width and DDR HS mode for eMMC

a4e0296

This is not the correct way to do this, but it gives a nice perf. boost

mpfs/emmcsd: Fix build issue with 8-bit HS mode

5158a1a

Fix build.yml

51991d6

Disable macOS builds for now.

risc-v/mpfs: ihc: Make IHC HSS workaround configurable

95b4d63

drivers/net/rpmsgdrv.c: Take netdev_register() return value into account

526ae42

drivers/net/rpmsgdrv.c: Support only TRANSFER commands

3ce90e5

All other commands are disabled in send_recv(). Signed-off-by: Jani Paalijarvi <[email protected]>

arch/risc-v/src/mpfs/mpfs_ihc.c: Increase RPMSG buffer size

5da097c

Signed-off-by: Jani Paalijarvi <[email protected]>

mpfs_ihc: Make Vring addresses configurable

8c5745b

arch/risc-v/src/mpfs/mpfs_fpga_canfd.c: Fix CONFIG_DEBUG_CAN_INFO ifd…

fcb4f6f

…ef and forward declare devif_loopback Signed-off-by: Jukka Laitinen <[email protected]>

boards/risc-v/mpfs/icicle/configs/canfd/defconfig: Normalize

e66ee29

Signed-off-by: Jukka Laitinen <[email protected]>

remove devif_loopback in canfd driver since it is now devif_poll func…

d5b4484

… that takes care of the need for loopback

arch/risc-v/src/mpfs/mpfs_ihc.c: Minor fixes

a9855a5

Remove unnecessary VQID shifting (16 -> 0). Give an error if RPTUN init fails.

Remove MPFS_IHC_LINUX_ON_HART4 from default configurations

9200709

Enable LINUX_ON_HART4 in rpmsg-ch2 defconfig of ICICLE board. Remove LINUX_ON_HART4 config from rpmsg-ch1 defconfig of ICICLE board.

arch/arm/src/stm32f7/stm32_ethernet.c: Fix "unused variable" warning

da7fcae

Fix build warning when CONFIG_STM32F7_AUTONEG is not set Signed-off-by: Jukka Laitinen <[email protected]>

arch/risc-v/src/mpfs/mpfs_userspace.c: Map MTIME into userspace reser…

62d55b7

…ved IO area in protected build Signed-off-by: Jukka Laitinen <[email protected]>

boards/risc-v/mpfs/icicle: Add USRIO area for userspace IO mappings

26f28ec

Signed-off-by: Jukka Laitinen <[email protected]>

Add mpfs crypto driver into nuttx build

765313f

Signed-off-by: Jukka Laitinen <[email protected]>

mpfs/Kconfig: fix typo on config file

7661ca1

pussuw and others added 19 commits October 17, 2023 19:40

mpfs_ethernet.c: Fix possible NULL de-reference

b53ad83

Fix case where NULL is de-referenced via tx/rx buffer or descriptor. Only 1 queue is currently set up for each, so the indices 1,2,3 are not valid and should not be handled.

mpfs_ethernet.c: Release tx descriptor and rx buffer properly

7e80998

Instead of releasing rx descriptor twice and tx buffer twice.

mpfs_head.S: Simplify clearing PMP

3866634

Initially clear PMP for all harts, this fixes random warm reset issues. Signed-off-by: Ville Juven <[email protected]>

arch/risc-v/src/mpfs/mpfs_ddr.c: Add read dq/dqs eye centering test

a96473f

After read training, check also that the eye is centered properly. Sometimes after the training the width is long enough, but it is not centered. Signed-off-by: Jukka Laitinen <[email protected]>

arch/risc-v/src/mpfs/mpfs_ddr.c: Clean up the TXDLY verify step

38a04e3

Just verify that the delay for the selected clock != 0 Signed-off-by: Jukka Laitinen <[email protected]>

riscv/riscv_pmp.c: fix broken TOR checks

4e4a88e

PMPCFG_A_TOR region may have zero size. The pmp configuration currently fails for zero-sized TOR. This patch bypasses such a restriction. Also replace log2ceil with LOG2_CEIL from lib/math32.h. Signed-off-by: Eero Nurkkala <[email protected]>

arch/risc-v: Remove unnecessary PMP kconfig options

76d2bd6

These options are just wrong and a result of misunderstanding of the Polarfire SoC spec. There are no feature limitations in the CPU PMP implementation -> remove any configuration options added.

mpfs_opensbi: Remove mpfs_opensbi_pmp_setup

cb8392f

The PMP setup should be done in the board specific code, at a much earlier stage. Granting all access is a security risk anyway.

mpfs_entrypoints.c: Open all memory from PMP for hart before booting

d2c09b2

Open PMP before the hart payload starts to execute

arch/mpfs: Add CONFIG_MPFS_BOARD_PMP option for PMP configuration

5722d68

This adds option to do PMP configuration via mpfs_board_pmp_setup instead of just opening up everything. In this case, it is up to the specific board to implement the PMP configuration in whichever way it sees fit.

arch/risc-v/src/mpfs/mpfs_serial.c: Allow switching uart output to co…

3e8ead3

…nsole off By setting "isconsole" to false, mpfs_serial stops outputting to console. This can be used to disable output to debug console in low level. Signed-off-by: Jukka Laitinen <[email protected]>

arch/risc-v/src/mpfs: Add hardware/mpfs_wdog.h

c74cd10

risc-v/mpfs: i2c: prevent out of bounds read access

a18cb51

priv->msgid may grow past its boundaries, causing struct i2c_msg_s *msg = &priv->msgv[priv->msgid] to read data out of boundaris. Signed-off-by: Eero Nurkkala <[email protected]>

risc-v/mpfs: tamper: refine tests

bc9dd58

Use only tests that will trigger a tamper event. Leave other tests outside. Signed-off-by: Eero Nurkkala <[email protected]>

pussuw requested review from gpoulios and eenurkka November 27, 2023 13:39

pussuw force-pushed the opensbi_regorganize branch from 604804e to bb125da Compare November 27, 2023 13:44

gpoulios approved these changes Nov 27, 2023

View reviewed changes

eenurkka approved these changes Nov 27, 2023

View reviewed changes

jlaitine force-pushed the master branch from 480e853 to 8276b09 Compare February 12, 2024 12:42

jlaitine force-pushed the master branch from a6a81be to 85fe8fc Compare September 25, 2024 08:07

pussuw force-pushed the master branch from 7aed9c3 to 890058d Compare November 28, 2024 09:52

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mpfs_opensbi: Re-organize SBI areas so that RW areas follow each other #185

mpfs_opensbi: Re-organize SBI areas so that RW areas follow each other #185

pussuw commented Nov 27, 2023

pussuw commented Nov 27, 2023

pussuw commented Nov 27, 2023

gpoulios left a comment

mpfs_opensbi: Re-organize SBI areas so that RW areas follow each other #185

Are you sure you want to change the base?

mpfs_opensbi: Re-organize SBI areas so that RW areas follow each other #185

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