intel_adsp: power: clock gating in idle

This patch add implementation of the dynamic clock gating for ACE platforms. Clock gating will be enabled/disabled by each DSP core before enter WAITI state. If clock gating is not desired, an application or other subsystem can prevent it via PM policy lock API. Signed-off-by: Tomasz Leman <[email protected]>
thesofproject · Nov 15, 2023 · e7a093e · e7a093e
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diff --git a/soc/xtensa/intel_adsp/Kconfig b/soc/xtensa/intel_adsp/Kconfig
@@ -113,4 +113,11 @@ config ADSP_IMR_CONTEXT_SAVE
 	  entering D3 state. Later this context can be used to FW restore
 	  when Host power up DSP again.
 
+config ADSP_CPU_DYNAMIC_CLOCK_GATING
+	bool "DSP clock gating in Idle"
+	help
+	  When true, FW will enable clock gating before core enter WAITI state
+	  (wait for interrupt) during idle. Clock gating will be disabled in which
+	  there is dependence on dependency to CCOUNT value or DSP clock interrupt.
+
 endif # SOC_FAMILY_INTEL_ADSP
diff --git a/soc/xtensa/intel_adsp/ace/power.c b/soc/xtensa/intel_adsp/ace/power.c
@@ -17,6 +17,7 @@
 #include <adsp_imr_layout.h>
 #include <zephyr/drivers/mm/mm_drv_intel_adsp_mtl_tlb.h>
 #include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/pm/policy.h>
 #include <mem_window.h>
 
 #define LPSRAM_MAGIC_VALUE      0x13579BDF
@@ -383,6 +384,15 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 void arch_cpu_idle(void)
 {
 	sys_trace_idle();
+
+#if CONFIG_ADSP_CPU_DYNAMIC_CLOCK_GATING
+	/* TODO: Add enum for substates (1 -> clock gating) */
+	if (pm_policy_state_lock_is_active(PM_STATE_ACTIVE, 1)) {
+		DSPCS.bootctl[arch_proc_id()].bctl |= DSPBR_BCTL_WAITIPCG;
+	} else {
+		DSPCS.bootctl[arch_proc_id()].bctl &= ~DSPBR_BCTL_WAITIPCG;
+	}
+#endif
 	wait_for_interrupt(0);
 }
 #endif