helper: add a condition before updating the component direction #8197
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At the pipeline reset stage, the direction of the components is not always known, resulting in a call to a field that is null and consequently a crash/timeout. Signed-off-by: Kwasowiec, Fabiola <[email protected]>
fkwasowi
requested review from
lgirdwood,
plbossart,
mmaka1,
lbetlej,
dbaluta and
kv2019i
as code owners
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Is this addressing a crash, that's caught by CI? Or only in your testing? Should this go to any stable branches too? |
| @@ -274,7 +274,7 @@ int ipc4_pipeline_prepare(struct ipc_comp_dev *ppl_icd, uint32_t cmd) | |||
| switch (status) { | |||
| case COMP_STATE_INIT: | |||
| tr_dbg(&ipc_tr, "pipeline %d: reset from init", ppl_icd->id); | |||
| ret = ipc4_pipeline_complete(ipc, ppl_icd->id); | |||
| ret = ipc4_pipeline_complete(ipc, ppl_icd->id, cmd); | |||
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@fkwasowi may I ask why we even need to invoke ipc4_pipeline_complete() during pipeline reset?
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This is still unanswered, but I assume this is a more complex. git blame shows this code has been here for a long, long time...
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I think this is the answer to the question: 8541d68
Due to this problem, the 09_oed_dmic_mute_unmute test is blocked. The issue is reported in the following HSD: https://hsdes.intel.com/appstore/article/#/18031254461 |
| @@ -274,7 +274,7 @@ int ipc4_pipeline_prepare(struct ipc_comp_dev *ppl_icd, uint32_t cmd) | |||
| switch (status) { | |||
| case COMP_STATE_INIT: | |||
| tr_dbg(&ipc_tr, "pipeline %d: reset from init", ppl_icd->id); | |||
| ret = ipc4_pipeline_complete(ipc, ppl_icd->id); | |||
| ret = ipc4_pipeline_complete(ipc, ppl_icd->id, cmd); | |||
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This is still unanswered, but I assume this is a more complex. git blame shows this code has been here for a long, long time...
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SOFCI TEST |
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Uh, sorry @fkwasowi I didn't notice you had pinged the CI already. But let's see that if this now completes... |
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SOFCI TEST |
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The one error in https://sof-ci.01.org/sofpr/PR8197/build13064/devicetest is a DUT issue. error in log: Proceeding with merge. |
At the pipeline reset stage, the direction of the components is not always known (example for the pipeline below), resulting in a call to a field that is null (src_buf->source->direction_set/src_buf->source->direction) and consequently a crash/timeout.