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Disable soft reset tests #388

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merged 1 commit into from
Dec 10, 2024
Merged

Disable soft reset tests #388

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137 changes: 69 additions & 68 deletions tests/api/test_chip.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -111,71 +111,72 @@ TEST(ApiChipTest, SimpleAPIShowcase) {
umd_cluster->get_num_host_channels(chip_id);
}

// This tests puts a specific core into reset and then deasserts it using default deassert value
// It reads back the risc reset reg to validate
TEST(ApiChipTest, DeassertRiscResetOnCore) {
std::unique_ptr<Cluster> umd_cluster = get_cluster();

if (umd_cluster == nullptr || umd_cluster->get_all_chips_in_cluster().empty()) {
GTEST_SKIP() << "No chips present on the system. Skipping test.";
}

tt_cxy_pair chip_core_coord = get_tensix_chip_core_coord(umd_cluster);

umd_cluster->assert_risc_reset_at_core(chip_core_coord);
umd_cluster->l1_membar(chip_core_coord.chip, "LARGE_WRITE_TLB");
umd_cluster->deassert_risc_reset_at_core(chip_core_coord);
umd_cluster->l1_membar(chip_core_coord.chip, "LARGE_WRITE_TLB");

uint32_t soft_reset_reg_addr = 0xFFB121B0;
uint32_t expected_risc_reset_val = static_cast<uint32_t>(TENSIX_DEASSERT_SOFT_RESET);
uint32_t risc_reset_val;
umd_cluster->read_from_device(&risc_reset_val, chip_core_coord, soft_reset_reg_addr, sizeof(uint32_t), "REG_TLB");
EXPECT_EQ(expected_risc_reset_val, risc_reset_val);
}

// This tests puts a specific core into reset and then specifies a legal deassert value
// It reads back the risc reset reg to validate
TEST(ApiChipTest, SpecifyLegalDeassertRiscResetOnCore) {
std::unique_ptr<Cluster> umd_cluster = get_cluster();

if (umd_cluster == nullptr || umd_cluster->get_all_chips_in_cluster().empty()) {
GTEST_SKIP() << "No chips present on the system. Skipping test.";
}

tt_cxy_pair chip_core_coord = get_tensix_chip_core_coord(umd_cluster);

umd_cluster->assert_risc_reset_at_core(chip_core_coord);
TensixSoftResetOptions deassert_val = ALL_TRISC_SOFT_RESET | TensixSoftResetOptions::STAGGERED_START;
umd_cluster->deassert_risc_reset_at_core(chip_core_coord, deassert_val);
umd_cluster->l1_membar(chip_core_coord.chip, "LARGE_WRITE_TLB");

uint32_t soft_reset_reg_addr = 0xFFB121B0;
uint32_t risc_reset_val;
umd_cluster->read_from_device(&risc_reset_val, chip_core_coord, soft_reset_reg_addr, sizeof(uint32_t), "REG_TLB");
EXPECT_EQ(static_cast<uint32_t>(deassert_val), risc_reset_val);
}

// // This tests puts a specific core into reset and then specifies an illegal deassert value
// // It reads back the risc reset reg to validate that reset reg is in a legal state
TEST(ApiChipTest, SpecifyIllegalDeassertRiscResetOnCore) {
std::unique_ptr<Cluster> umd_cluster = get_cluster();

if (umd_cluster == nullptr || umd_cluster->get_all_chips_in_cluster().empty()) {
GTEST_SKIP() << "No chips present on the system. Skipping test.";
}

tt_cxy_pair chip_core_coord = get_tensix_chip_core_coord(umd_cluster);

umd_cluster->assert_risc_reset_at_core(chip_core_coord);

TensixSoftResetOptions deassert_val = static_cast<TensixSoftResetOptions>(0xDEADBEEF);
umd_cluster->deassert_risc_reset_at_core(chip_core_coord, deassert_val);
umd_cluster->l1_membar(chip_core_coord.chip, "LARGE_WRITE_TLB");

uint32_t soft_reset_reg_addr = 0xFFB121B0;
uint32_t risc_reset_val;
umd_cluster->read_from_device(&risc_reset_val, chip_core_coord, soft_reset_reg_addr, sizeof(uint32_t), "REG_TLB");
uint32_t expected_deassert_val = static_cast<uint32_t>(deassert_val & ALL_TENSIX_SOFT_RESET);
EXPECT_EQ(risc_reset_val, expected_deassert_val);
}
// TODO: Re-enable once we debug why it doesn't work #362
// // This tests puts a specific core into reset and then deasserts it using default deassert value
// // It reads back the risc reset reg to validate
// TEST(ApiChipTest, DeassertRiscResetOnCore) {
// std::unique_ptr<Cluster> umd_cluster = get_cluster();

// if (umd_cluster == nullptr || umd_cluster->get_all_chips_in_cluster().empty()) {
// GTEST_SKIP() << "No chips present on the system. Skipping test.";
// }

// tt_cxy_pair chip_core_coord = get_tensix_chip_core_coord(umd_cluster);

// umd_cluster->assert_risc_reset_at_core(chip_core_coord);
// umd_cluster->l1_membar(chip_core_coord.chip, "LARGE_WRITE_TLB");
// umd_cluster->deassert_risc_reset_at_core(chip_core_coord);
// umd_cluster->l1_membar(chip_core_coord.chip, "LARGE_WRITE_TLB");

// uint32_t soft_reset_reg_addr = 0xFFB121B0;
// uint32_t expected_risc_reset_val = static_cast<uint32_t>(TENSIX_DEASSERT_SOFT_RESET);
// uint32_t risc_reset_val;
// umd_cluster->read_from_device(&risc_reset_val, chip_core_coord, soft_reset_reg_addr, sizeof(uint32_t),
// "REG_TLB"); EXPECT_EQ(expected_risc_reset_val, risc_reset_val);
// }

// // This tests puts a specific core into reset and then specifies a legal deassert value
// // It reads back the risc reset reg to validate
// TEST(ApiChipTest, SpecifyLegalDeassertRiscResetOnCore) {
// std::unique_ptr<Cluster> umd_cluster = get_cluster();

// if (umd_cluster == nullptr || umd_cluster->get_all_chips_in_cluster().empty()) {
// GTEST_SKIP() << "No chips present on the system. Skipping test.";
// }

// tt_cxy_pair chip_core_coord = get_tensix_chip_core_coord(umd_cluster);

// umd_cluster->assert_risc_reset_at_core(chip_core_coord);
// TensixSoftResetOptions deassert_val = ALL_TRISC_SOFT_RESET | TensixSoftResetOptions::STAGGERED_START;
// umd_cluster->deassert_risc_reset_at_core(chip_core_coord, deassert_val);
// umd_cluster->l1_membar(chip_core_coord.chip, "LARGE_WRITE_TLB");

// uint32_t soft_reset_reg_addr = 0xFFB121B0;
// uint32_t risc_reset_val;
// umd_cluster->read_from_device(&risc_reset_val, chip_core_coord, soft_reset_reg_addr, sizeof(uint32_t),
// "REG_TLB"); EXPECT_EQ(static_cast<uint32_t>(deassert_val), risc_reset_val);
// }

// // // This tests puts a specific core into reset and then specifies an illegal deassert value
// // // It reads back the risc reset reg to validate that reset reg is in a legal state
// TEST(ApiChipTest, SpecifyIllegalDeassertRiscResetOnCore) {
// std::unique_ptr<Cluster> umd_cluster = get_cluster();

// if (umd_cluster == nullptr || umd_cluster->get_all_chips_in_cluster().empty()) {
// GTEST_SKIP() << "No chips present on the system. Skipping test.";
// }

// tt_cxy_pair chip_core_coord = get_tensix_chip_core_coord(umd_cluster);

// umd_cluster->assert_risc_reset_at_core(chip_core_coord);

// TensixSoftResetOptions deassert_val = static_cast<TensixSoftResetOptions>(0xDEADBEEF);
// umd_cluster->deassert_risc_reset_at_core(chip_core_coord, deassert_val);
// umd_cluster->l1_membar(chip_core_coord.chip, "LARGE_WRITE_TLB");

// uint32_t soft_reset_reg_addr = 0xFFB121B0;
// uint32_t risc_reset_val;
// umd_cluster->read_from_device(&risc_reset_val, chip_core_coord, soft_reset_reg_addr, sizeof(uint32_t),
// "REG_TLB"); uint32_t expected_deassert_val = static_cast<uint32_t>(deassert_val & ALL_TENSIX_SOFT_RESET);
// EXPECT_EQ(risc_reset_val, expected_deassert_val);
// }
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