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Implement soc descriptor CoreCoord API
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@pjanevskiTT
pjanevskiTT committed Dec 11, 2024
1 parent 51ee2e5 commit fc89b2e
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Showing 9 changed files with 637 additions and 50 deletions.
3 changes: 3 additions & 0 deletions device/api/umd/device/blackhole_coordinate_manager.h
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Expand Up @@ -34,6 +34,9 @@ class BlackholeCoordinateManager : public CoordinateManager {
void fill_pcie_physical_translated_mapping() override;
void fill_dram_physical_translated_mapping() override;

void fill_tensix_core_structures() override;
void fill_dram_core_structures() override;

private:
void map_column_of_dram_banks(const size_t start_bank, const size_t end_bank, const size_t x_coord);
};
32 changes: 27 additions & 5 deletions device/api/umd/device/coordinate_manager.h
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Expand Up @@ -42,6 +42,12 @@ class CoordinateManager {

tt::umd::CoreCoord to(const tt::umd::CoreCoord core_coord, const CoordSystem coord_system);

std::vector<tt::umd::CoreCoord> get_cores(const CoreType core_type) const;
tt_xy_pair get_grid_size(const CoreType core_type) const;

std::vector<tt::umd::CoreCoord> get_harvested_cores(const CoreType core_type) const;
tt_xy_pair get_harvested_grid_size(const CoreType core_type) const;

virtual ~CoordinateManager() = default;

private:
Expand Down Expand Up @@ -74,6 +80,13 @@ class CoordinateManager {
void identity_map_physical_cores();
void add_core_translation(const tt::umd::CoreCoord& core_coord, const tt_xy_pair& physical_pair);

void fill_core_structures();
virtual void fill_tensix_core_structures();
virtual void fill_dram_core_structures();
virtual void fill_eth_core_structures();
virtual void fill_arc_core_structures();
virtual void fill_pcie_core_structures();

/*
* Fills the logical to translated mapping for the tensix cores.
* By default, translated coordinates are the same as physical coordinates.
Expand Down Expand Up @@ -121,22 +134,31 @@ class CoordinateManager {
std::map<tt::umd::CoreCoord, tt_xy_pair> to_physical_map;
std::map<std::pair<tt_xy_pair, CoordSystem>, tt::umd::CoreCoord> from_physical_map;

const tt_xy_pair tensix_grid_size;
tt_xy_pair tensix_grid_size;
const std::vector<tt_xy_pair>& tensix_cores;
std::vector<tt::umd::CoreCoord> unharvested_tensix_cores;
tt_xy_pair harvested_tensix_grid_size;
std::vector<tt::umd::CoreCoord> harvested_tensix_cores;
size_t tensix_harvesting_mask;

const tt_xy_pair dram_grid_size;
tt_xy_pair dram_grid_size;
const std::vector<tt_xy_pair>& dram_cores;
std::vector<tt::umd::CoreCoord> unharvested_dram_cores;
tt_xy_pair harvested_dram_grid_size;
std::vector<tt::umd::CoreCoord> harvested_dram_cores;
size_t dram_harvesting_mask;

const tt_xy_pair eth_grid_size;
tt_xy_pair eth_grid_size;
const std::vector<tt_xy_pair>& eth_cores;
std::vector<tt::umd::CoreCoord> unharvested_eth_cores;

const tt_xy_pair arc_grid_size;
tt_xy_pair arc_grid_size;
const std::vector<tt_xy_pair>& arc_cores;
std::vector<tt::umd::CoreCoord> unharvested_arc_cores;

const tt_xy_pair pcie_grid_size;
tt_xy_pair pcie_grid_size;
const std::vector<tt_xy_pair>& pcie_cores;
std::vector<tt::umd::CoreCoord> unharvested_pcie_cores;
};

// friend
85 changes: 48 additions & 37 deletions device/api/umd/device/tt_soc_descriptor.h
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Expand Up @@ -46,42 +46,6 @@ struct CoreDescriptor {
*/
class tt_SocDescriptor {
public:
tt::ARCH arch;
tt_xy_pair grid_size;
tt_xy_pair physical_grid_size;
tt_xy_pair worker_grid_size;
std::unordered_map<tt_xy_pair, CoreDescriptor> cores;
std::vector<tt_xy_pair> arc_cores;
std::vector<tt_xy_pair> workers;
std::vector<tt_xy_pair> harvested_workers;
std::vector<tt_xy_pair> pcie_cores;
std::unordered_map<int, int> worker_log_to_routing_x;
std::unordered_map<int, int> worker_log_to_routing_y;
std::unordered_map<int, int> routing_x_to_worker_x;
std::unordered_map<int, int> routing_y_to_worker_y;
std::vector<std::vector<tt_xy_pair>> dram_cores; // per channel list of dram cores
std::unordered_map<tt_xy_pair, std::tuple<int, int>> dram_core_channel_map; // map dram core to chan/subchan
std::vector<tt_xy_pair> ethernet_cores; // ethernet cores (index == channel id)
std::unordered_map<tt_xy_pair, int> ethernet_core_channel_map;
std::vector<std::size_t> trisc_sizes; // Most of software stack assumes same trisc size for whole chip..
std::string device_descriptor_file_path = std::string("");

bool has(tt_xy_pair input) { return cores.find(input) != cores.end(); }

int overlay_version;
int unpacker_version;
int dst_size_alignment;
int packer_version;
int worker_l1_size;
int eth_l1_size;
bool noc_translation_id_enabled;
uint64_t dram_bank_size;

int get_num_dram_channels() const;
bool is_worker_core(const tt_xy_pair &core) const;
tt_xy_pair get_core_for_dram_channel(int dram_chan, int subchannel) const;
bool is_ethernet_core(const tt_xy_pair &core) const;

// Default constructor. Creates uninitialized object with public access to all of its attributes.
tt_SocDescriptor() = default;
// Constructor used to build object from device descriptor file.
Expand Down Expand Up @@ -122,15 +86,62 @@ class tt_SocDescriptor {
coordinate_manager(other.coordinate_manager) {}

// CoreCoord conversions.
tt::umd::CoreCoord to(const tt::umd::CoreCoord core_coord, const CoordSystem coord_system);
tt::umd::CoreCoord to(const tt::umd::CoreCoord core_coord, const CoordSystem coord_system) const;

static std::string get_soc_descriptor_path(tt::ARCH arch);

std::vector<tt::umd::CoreCoord> get_cores(const CoreType core_type) const;
std::vector<tt::umd::CoreCoord> get_harvested_cores(const CoreType core_type) const;
tt_xy_pair get_grid_size(const CoreType core_type) const;
tt_xy_pair get_harvested_grid_size(const CoreType core_type) const;

int get_num_dram_channels() const;

bool is_worker_core(const tt_xy_pair &core) const;

tt_xy_pair get_core_for_dram_channel(int dram_chan, int subchannel) const;

tt::umd::CoreCoord get_dram_core_for_channel(int dram_chan, int subchannel) const;
tt::umd::CoreCoord get_dram_core(uint32_t dram_chan, uint32_t subchannel) const;

bool is_ethernet_core(const tt_xy_pair &core) const;

tt::ARCH arch;
tt_xy_pair grid_size;
tt_xy_pair physical_grid_size;
tt_xy_pair worker_grid_size;
std::unordered_map<tt_xy_pair, CoreDescriptor> cores;
std::vector<tt_xy_pair> arc_cores;
std::vector<tt_xy_pair> workers;
std::vector<tt_xy_pair> harvested_workers;
std::vector<tt_xy_pair> pcie_cores;
std::unordered_map<int, int> worker_log_to_routing_x;
std::unordered_map<int, int> worker_log_to_routing_y;
std::unordered_map<int, int> routing_x_to_worker_x;
std::unordered_map<int, int> routing_y_to_worker_y;
std::vector<std::vector<tt_xy_pair>> dram_cores; // per channel list of dram cores
std::unordered_map<tt_xy_pair, std::tuple<int, int>> dram_core_channel_map; // map dram core to chan/subchan
std::vector<tt_xy_pair> ethernet_cores; // ethernet cores (index == channel id)
std::unordered_map<tt_xy_pair, int> ethernet_core_channel_map;
std::vector<std::size_t> trisc_sizes; // Most of software stack assumes same trisc size for whole chip..
std::string device_descriptor_file_path = std::string("");

int overlay_version;
int unpacker_version;
int dst_size_alignment;
int packer_version;
int worker_l1_size;
int eth_l1_size;
bool noc_translation_id_enabled;
uint64_t dram_bank_size;

private:
void create_coordinate_manager(const std::size_t tensix_harvesting_mask, const std::size_t dram_harvesting_mask);
void load_core_descriptors_from_device_descriptor(YAML::Node &device_descriptor_yaml);
void load_soc_features_from_device_descriptor(YAML::Node &device_descriptor_yaml);

static tt_xy_pair calculate_grid_size(const std::vector<tt_xy_pair> &cores);

// TODO: change this to unique pointer as soon as copying of tt_SocDescriptor
// is not needed anymore. Soc descriptor and coordinate manager should be
// created once per chip.
Expand Down
57 changes: 57 additions & 0 deletions device/blackhole/blackhole_coordinate_manager.cpp
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Expand Up @@ -179,6 +179,25 @@ void BlackholeCoordinateManager::map_column_of_dram_banks(
}

void BlackholeCoordinateManager::fill_dram_physical_translated_mapping() {
if (dram_grid_size.x < blackhole::NUM_DRAM_BANKS) {
// If the number of DRAM banks is less than num dram banks for standard SOC for Blackhole,
// map the translated DRAM cores to be the same as physical DRAM cores.
// TODO: Figure out how DRAM is going to be mapped to translated coordinates when there is less DRAM banks.
for (size_t x = 0; x < dram_grid_size.x; x++) {
for (size_t y = 0; y < dram_grid_size.y; y++) {
const CoreCoord logical_dram_core = CoreCoord(x, y, CoreType::DRAM, CoordSystem::LOGICAL);
const tt_xy_pair physical_dram_core = to_physical_map[logical_dram_core];

CoreCoord translated_dram_core =
CoreCoord(physical_dram_core.x, physical_dram_core.y, CoreType::DRAM, CoordSystem::TRANSLATED);
to_physical_map[translated_dram_core] = physical_dram_core;
from_physical_map[{{physical_dram_core.x, physical_dram_core.y}, CoordSystem::TRANSLATED}] =
translated_dram_core;
}
}
return;
}

const std::vector<size_t> harvested_banks = CoordinateManager::get_harvested_indices(dram_harvesting_mask);

if (harvested_banks.empty()) {
Expand Down Expand Up @@ -233,3 +252,41 @@ void BlackholeCoordinateManager::fill_dram_physical_translated_mapping() {
add_core_translation(translated_coord, physical_core);
}
}

void BlackholeCoordinateManager::fill_tensix_core_structures() {
std::vector<size_t> harvested_x_coords = get_harvested_indices(tensix_harvesting_mask);
for (size_t y = 0; y < tensix_grid_size.y; y++) {
for (size_t x = 0; x < tensix_grid_size.x; x++) {
const tt_xy_pair core = tensix_cores[y * tensix_grid_size.x + x];
CoreCoord core_coord(core.x, core.y, CoreType::TENSIX, CoordSystem::PHYSICAL);
if (std::find(harvested_x_coords.begin(), harvested_x_coords.end(), x) == harvested_x_coords.end()) {
unharvested_tensix_cores.push_back(core_coord);
} else {
harvested_tensix_cores.push_back(core_coord);
}
}
}
const size_t num_harvested_x = harvested_x_coords.size();
tensix_grid_size.x -= num_harvested_x;
harvested_tensix_grid_size.x = num_harvested_x;
harvested_tensix_grid_size.y = tensix_grid_size.y;
}

void BlackholeCoordinateManager::fill_dram_core_structures() {
std::vector<size_t> harvested_banks = get_harvested_indices(dram_harvesting_mask);
for (size_t bank = 0; bank < dram_grid_size.x; bank++) {
for (size_t port = 0; port < dram_grid_size.y; port++) {
const tt_xy_pair core = dram_cores[bank * dram_grid_size.y + port];
CoreCoord core_coord(core.x, core.y, CoreType::DRAM, CoordSystem::PHYSICAL);
if (std::find(harvested_banks.begin(), harvested_banks.end(), bank) == harvested_banks.end()) {
unharvested_dram_cores.push_back(core_coord);
} else {
harvested_dram_cores.push_back(core_coord);
}
}
}
const size_t num_harvested_banks = harvested_banks.size();
dram_grid_size.x -= num_harvested_banks;
harvested_dram_grid_size.x = num_harvested_banks;
harvested_dram_grid_size.y = dram_grid_size.y;
}
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