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GELU Op implementation
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azecevicTT committed Oct 31, 2024
1 parent caa7b90 commit 368fc3d
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Showing 10 changed files with 59 additions and 1 deletion.
7 changes: 7 additions & 0 deletions include/ttmlir/Dialect/TTIR/IR/TTIROps.td
Original file line number Diff line number Diff line change
Expand Up @@ -210,6 +210,13 @@ def TTIR_CosOp: TTIR_ElementwiseUnaryOp<"cos"> {
}];
}

def TTIR_GeluOp: TTIR_ElementwiseUnaryOp<"gelu"> {
let summary = "Eltwise GELU op.";
let description = [{
Eltwise GELU operation.
}];
}

def TTIR_LogicalNotOp: TTIR_ElementwiseUnaryOp<"logical_not"> {
let summary = "Eltwise logical not op.";
let description = [{
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7 changes: 7 additions & 0 deletions include/ttmlir/Dialect/TTNN/IR/TTNNOps.td
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Expand Up @@ -197,6 +197,13 @@ def TTNN_ExpOp : TTNN_ElementwiseUnaryOp<"exp"> {
}];
}

def TTNN_GeluOp: TTNN_ElementwiseUnaryOp<"gelu"> {
let summary = "Eltwise GELU.";
let description = [{
Eltwise GELU operation.
}];
}

def TTNN_LogicalNotOp: TTNN_ElementwiseUnaryOp<"logical_not"> {
let summary = "Eltwise logical not op.";
let description = [{
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3 changes: 2 additions & 1 deletion include/ttmlir/Target/TTNN/program.fbs
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Expand Up @@ -85,7 +85,8 @@ enum EltwiseOpType: uint32 {
Minimum = 24,
Ceil = 25,
Sin = 26,
Cos = 27
Cos = 27,
Gelu = 28
}

table EltwiseOp {
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1 change: 1 addition & 0 deletions lib/Conversion/TTIRToTTNN/TTIRToTTNN.cpp
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Expand Up @@ -823,6 +823,7 @@ void populateTTIRToTTNNPatterns(MLIRContext *ctx, RewritePatternSet &patterns,
ElementwiseOpConversionPattern<ttir::MinimumOp, ttnn::MinimumOp>,
ElementwiseOpConversionPattern<ttir::NegOp, ttnn::NegOp>,
ElementwiseOpConversionPattern<ttir::ReluOp, ttnn::ReluOp>,
ElementwiseOpConversionPattern<ttir::GeluOp, ttnn::GeluOp>,
ElementwiseOpConversionPattern<ttir::SqrtOp, ttnn::SqrtOp>,
ElementwiseOpConversionPattern<ttir::RsqrtOp, ttnn::RsqrtOp>,
ElementwiseOpConversionPattern<ttir::SigmoidOp, ttnn::SigmoidOp>,
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1 change: 1 addition & 0 deletions lib/Conversion/TTNNToEmitC/TTNNToEmitC.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -619,6 +619,7 @@ void populateTTNNToEmitCPatterns(mlir::MLIRContext *ctx,
DefaultOpConversionPattern<ttnn::LogicalNotOp>,
DefaultOpConversionPattern<ttnn::NegOp>,
DefaultOpConversionPattern<ttnn::ReluOp>,
DefaultOpConversionPattern<ttnn::GeluOp>,
DefaultOpConversionPattern<ttnn::SqrtOp>,
DefaultOpConversionPattern<ttnn::RsqrtOp>,
DefaultOpConversionPattern<ttnn::SigmoidOp>,
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5 changes: 5 additions & 0 deletions lib/Target/TTNN/TTNNToFlatbuffer.cpp
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Expand Up @@ -347,6 +347,8 @@ createEltwiseOp(FlatbufferObjectCache &cache, EltwiseOp op) {
type = ::tt::target::ttnn::EltwiseOpType::Cos;
} else if constexpr (std::is_same_v<EltwiseOp, SinOp>) {
type = ::tt::target::ttnn::EltwiseOpType::Sin;
} else if constexpr (std::is_same_v<EltwiseOp, GeluOp>) {
type = ::tt::target::ttnn::EltwiseOpType::Gelu;
} else {
llvm_unreachable("unhandled EltwiseOp");
}
Expand Down Expand Up @@ -661,6 +663,9 @@ emitTTNNOperation(FlatbufferObjectCache &cache, Operation *op,
if (auto sinOp = dyn_cast<SinOp>(op); sinOp) {
return createOperation(cache, createEltwiseOp(cache, sinOp), debugString);
}
if (auto geluOp = dyn_cast<GeluOp>(op); geluOp) {
return createOperation(cache, createEltwiseOp(cache, geluOp), debugString);
}

llvm_unreachable("unhandled op in emitTTNNOperation");
}
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4 changes: 4 additions & 0 deletions runtime/lib/ttnn/operations/eltwise/unary.cpp
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Expand Up @@ -92,6 +92,10 @@ void run(const ::tt::target::ttnn::EltwiseOp *op, ProgramContext &context) {
runEltwiseUnaryOP(op, tensorPool, ::ttnn::cos);
break;
}
case ::tt::target::ttnn::EltwiseOpType::Gelu: {
runEltwiseUnaryWithFastAndApproximateModeOP(op, tensorPool, ::ttnn::gelu);
break;
}
case ::tt::target::ttnn::EltwiseOpType::LogicalNot: {
runEltwiseUnaryOP(op, tensorPool, ::ttnn::logical_not);
break;
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11 changes: 11 additions & 0 deletions test/ttmlir/Dialect/TTNN/eltwise/unary/gelu/simple_gelu.mlir
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@@ -0,0 +1,11 @@
// RUN: ttmlir-opt --ttir-to-ttnn-backend-pipeline %s | FileCheck %s
#any_device = #tt.operand_constraint<dram|l1|scalar|tile|any_device|any_device_tile>
module attributes {} {
func.func @forward(%arg0: tensor<64x128xf32>) -> tensor<64x128xf32> {
// CHECK: %[[C:.*]] = "ttnn.empty"[[C:.*]]
%0 = tensor.empty() : tensor<64x128xf32>
// CHECK: %[[C:.*]] = "ttnn.gelu"[[C:.*]]
%1 = "ttir.gelu"(%arg0, %0) <{operandSegmentSizes = array<i32: 1, 1>, operand_constraints = [#any_device, #any_device]}> : (tensor<64x128xf32>, tensor<64x128xf32>) -> tensor<64x128xf32>
return %1 : tensor<64x128xf32>
}
}
13 changes: 13 additions & 0 deletions test/ttmlir/Silicon/TTNN/perf_unit/test_perf_gelu.mlir
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@@ -0,0 +1,13 @@
// RUN: ttmlir-opt --ttir-to-ttnn-backend-pipeline="system-desc-path=%system_desc_path%" %s > %t.mlir
// RUN: FileCheck %s --input-file=%t.mlir
// RUN: ttmlir-translate --ttnn-to-flatbuffer %t.mlir > %t.ttnn
#any_device = #tt.operand_constraint<dram|l1|scalar|tile|any_device|any_device_tile>
#any_device_tile = #tt.operand_constraint<dram|l1|tile|any_device_tile>

func.func @gelu(%arg0: tensor<64x128xf32>) -> tensor<64x128xf32> {
// CHECK: %[[C:.*]] = "ttnn.empty"[[C:.*]]
%0 = tensor.empty() : tensor<64x128xf32>
// CHECK: %[[C:.*]] = "ttnn.gelu"[[C:.*]]
%1 = "ttir.gelu"(%arg0, %0) <{operandSegmentSizes = array<i32: 1, 1>, operand_constraints = [#any_device, #any_device]}> : (tensor<64x128xf32>, tensor<64x128xf32>) -> tensor<64x128xf32>
return %1 : tensor<64x128xf32>
}
8 changes: 8 additions & 0 deletions test/ttmlir/Silicon/TTNN/simple_eltwise.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -183,3 +183,11 @@ func.func @typecast(%arg0: tensor<64x128xf32>) -> tensor<64x128xbf16> {
%1 = "ttir.typecast"(%arg0, %0) <{operandSegmentSizes = array<i32: 1, 1>, operand_constraints = [#any_device, #any_device]}> : (tensor<64x128xf32>, tensor<64x128xbf16>) -> tensor<64x128xbf16>
return %1 : tensor<64x128xbf16>
}

func.func @gelu(%arg0: tensor<64x128xf32>) -> tensor<64x128xf32> {
// CHECK: %[[C:.*]] = "ttnn.empty"[[C:.*]]
%0 = tensor.empty() : tensor<64x128xf32>
// CHECK: %[[C:.*]] = "ttnn.gelu"[[C:.*]]
%1 = "ttir.gelu"(%arg0, %0) <{operandSegmentSizes = array<i32: 1, 1>, operand_constraints = [#any_device, #any_device]}> : (tensor<64x128xf32>, tensor<64x128xf32>) -> tensor<64x128xf32>
return %1 : tensor<64x128xf32>
}

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