#11789: Fix ierisc mailboxes/memory map

Some bad values just happened to work, sizes now line up
tenstorrent · Sep 27, 2024 · d0a9df7 · d0a9df7
1 parent 006e861
commit d0a9df7
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Showing 5 changed files with 21 additions and 8 deletions.
diff --git a/tt_metal/hostdevcommon/common_runtime_address_map.h b/tt_metal/hostdevcommon/common_runtime_address_map.h
@@ -39,7 +39,7 @@ static_assert (PROFILER_FULL_HOST_BUFFER_SIZE_PER_RISC > kernel_profiler::PROFIL
 constexpr static std::uint32_t L1_KERNEL_CONFIG_BASE = MEM_MAP_END;
 constexpr static std::uint32_t L1_KERNEL_CONFIG_SIZE = 4 * 1024 + 256 + 128 + 512;
 
-constexpr static std::uint32_t IDLE_ERISC_L1_KERNEL_CONFIG_BASE = 32 * 1024;
+constexpr static std::uint32_t IDLE_ERISC_L1_KERNEL_CONFIG_BASE = MEM_IERISC_MAP_END;
 
 constexpr static std::uint32_t NUM_CIRCULAR_BUFFERS = 32;
 constexpr static std::uint32_t UINT32_WORDS_PER_CIRCULAR_BUFFER_CONFIG = 4;

diff --git a/tt_metal/hw/inc/blackhole/dev_mem_map.h b/tt_metal/hw/inc/blackhole/dev_mem_map.h
@@ -101,11 +101,15 @@
 // IERISC memory map
 #define MEM_IERISC_LOCAL_SIZE (8 * 1024)
 #define MEM_IERISC_FIRMWARE_SIZE (24 * 1024)
-#define MEM_IERISC_MAILBOX_BASE 1024
-#define MEM_IERISC_MAILBOX_END (MEM_IERISC_MAILBOX_BASE + 128)
+#define MEM_IERISC_MAILBOX_BASE 32
+#define MEM_IERISC_MAILBOX_SIZE 3072
+#define MEM_IERISC_MAILBOX_END (MEM_IERISC_MAILBOX_BASE + MEM_IERISC_MAILBOX_SIZE)
+// TODO: this should be tightly packed against MAILBOX_END but that causes
+// problems w/ back to back runs, leaving the padding for now
 #define MEM_IERISC_FIRMWARE_BASE 8192
-#define MEM_IERISC_INIT_LOCAL_L1_BASE_SCRATCH (MEM_IERISC_FIRMWARE_BASE + MEM_IERISC_FIRMWARE_SIZE)
-#define MEM_IERISC_STACK_SIZE 768
+#define MEM_IERISC_MAP_END (MEM_IERISC_FIRMWARE_BASE + MEM_IERISC_FIRMWARE_SIZE)
+#define MEM_IERISC_INIT_LOCAL_L1_BASE_SCRATCH MEM_IERISC_MAP_END
+#define MEM_IERISC_STACK_SIZE 1024
 #define MEM_IERISC_STACK_BASE (MEM_LOCAL_BASE + MEM_IERISC_LOCAL_SIZE - MEM_IERISC_STACK_SIZE)
 
 #define MEM_IERISC_KERNEL_PAD 28
diff --git a/tt_metal/hw/inc/dev_msgs.h b/tt_metal/hw/inc/dev_msgs.h
@@ -292,6 +292,7 @@ static_assert(sizeof(watcher_msg_t) % sizeof(uint32_t) == 0);
 static_assert(sizeof(kernel_config_msg_t) % sizeof(uint32_t) == 0);
 static_assert(sizeof(core_info_msg_t) % sizeof(uint32_t) == 0);
 
+// TODO: move these checks into the HAL?
 #ifndef TENSIX_FIRMWARE
 // Validate assumptions on mailbox layout on host compile
 // Constexpr definitions allow for printing of breaking values at compile time
@@ -307,6 +308,8 @@ static constexpr uint32_t ETH_LAUNCH_CHECK = (eth_l1_mem::address_map::ERISC_MEM
 static constexpr uint32_t ETH_PROFILER_CHECK = (eth_l1_mem::address_map::ERISC_MEM_MAILBOX_BASE  + offsetof(mailboxes_t, profiler)) % TT_ARCH_MAX_NOC_WRITE_ALIGNMENT;
 static_assert( ETH_LAUNCH_CHECK == 0);
 static_assert( ETH_PROFILER_CHECK == 0);
+static_assert(MEM_IERISC_FIRMWARE_BASE % TT_ARCH_MAX_NOC_WRITE_ALIGNMENT == 0);
+static_assert(MEM_IERISC_MAILBOX_BASE + sizeof(mailboxes_t) < MEM_IERISC_MAILBOX_END);
 #else
 static_assert(MEM_MAILBOX_BASE + sizeof(mailboxes_t) < MEM_MAILBOX_END);
 static constexpr uint32_t TENSIX_LAUNCH_CHECK = (MEM_MAILBOX_BASE + offsetof(mailboxes_t, launch)) % TT_ARCH_MAX_NOC_WRITE_ALIGNMENT;

diff --git a/tt_metal/hw/inc/grayskull/dev_mem_map.h b/tt_metal/hw/inc/grayskull/dev_mem_map.h
@@ -113,6 +113,7 @@
 #define MEM_IERISC_MAILBOX_BASE 0
 #define MEM_IERISC_MAILBOX_END 0
 #define MEM_IERISC_FIRMWARE_BASE 0
+#define MEM_IERISC_MAP_END 0
 #define MEM_IERISC_INIT_LOCAL_L1_BASE_SCRATCH 0
 #define MEM_IERISC_STACK_SIZE 0
 

diff --git a/tt_metal/hw/inc/wormhole/dev_mem_map.h b/tt_metal/hw/inc/wormhole/dev_mem_map.h
@@ -111,10 +111,15 @@
 // IERISC memory map
 #define MEM_IERISC_LOCAL_SIZE (4 * 1024)
 #define MEM_IERISC_FIRMWARE_SIZE (16 * 1024)
-#define MEM_IERISC_MAILBOX_BASE 1024
-#define MEM_IERISC_MAILBOX_END (MEM_IERISC_MAILBOX_BASE + 128)
+#define MEM_IERISC_MAILBOX_BASE 32
+// TODO: reduce this when mailbox sizes are core type aware for some members (eg watcher/dprint)
+#define MEM_IERISC_MAILBOX_SIZE 3072
+#define MEM_IERISC_MAILBOX_END (MEM_IERISC_MAILBOX_BASE + MEM_IERISC_MAILBOX_SIZE)
+// TODO: this should be tightly packed against MAILBOX_END but that causes
+// problems w/ back to back runs, leaving the padding for now
 #define MEM_IERISC_FIRMWARE_BASE 8192
-#define MEM_IERISC_INIT_LOCAL_L1_BASE_SCRATCH (MEM_IERISC_FIRMWARE_BASE + MEM_IERISC_FIRMWARE_SIZE)
+#define MEM_IERISC_MAP_END (MEM_IERISC_FIRMWARE_BASE + MEM_IERISC_FIRMWARE_SIZE)
+#define MEM_IERISC_INIT_LOCAL_L1_BASE_SCRATCH MEM_IERISC_MAP_END
 #define MEM_IERISC_STACK_SIZE 1024
 #define MEM_IERISC_STACK_BASE (MEM_LOCAL_BASE + MEM_IERISC_LOCAL_SIZE - MEM_IERISC_STACK_SIZE)