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#4984: Consolidate linker scripts
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In prep for having firmware/kernel specific linker scripts
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@pgkeller
pgkeller committed Jul 30, 2024
1 parent 9e2819e commit b0c19a7
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Showing 22 changed files with 75 additions and 412 deletions.
2 changes: 1 addition & 1 deletion tt_metal/common/metal_soc_descriptor.cpp
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Expand Up @@ -372,7 +372,7 @@ void metal_SocDescriptor::generate_physical_routing_to_profiler_flat_id() {
// virtual coordinates because UMD APIs expect virtual coordinates.
metal_SocDescriptor::metal_SocDescriptor(const tt_SocDescriptor& other, uint32_t harvesting_mask) :
tt_SocDescriptor(other) {
this->trisc_sizes = {MEM_TRISC0_SIZE, MEM_TRISC1_SIZE, MEM_TRISC2_SIZE}; // TODO: Read trisc size from yaml
this->trisc_sizes = {MEM_TRISC0_FIRMWARE_SIZE, MEM_TRISC1_FIRMWARE_SIZE, MEM_TRISC2_FIRMWARE_SIZE}; // TODO: Read trisc size from yaml
this->generate_physical_descriptors_from_virtual(harvesting_mask);
this->load_dram_metadata_from_device_descriptor();
this->generate_logical_eth_coords_mapping();
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7 changes: 4 additions & 3 deletions tt_metal/hw/CMakeLists.txt
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Expand Up @@ -6,7 +6,7 @@ set(CORES
trisc0
trisc1
trisc2
idle-erisc
ierisc
)

if("$ENV{ARCH_NAME}" STREQUAL "wormhole_b0")
Expand All @@ -19,13 +19,14 @@ endif()

foreach(CORE IN LISTS CORES)
set(HW_OUTPUT_FILE "${HW_OUTPUT_DIR}/${CORE}.ld")
string(TOUPPER ${CORE} CORE_DEFINE)

# custom command to preprocess/generate the output file
add_custom_command(
OUTPUT ${HW_OUTPUT_FILE}
COMMAND ${CMAKE_COMMAND} -E make_directory ${HW_OUTPUT_DIR}
COMMAND ${CMAKE_CXX_COMPILER} -I${HW_INCLUDES} -E -P -x c -o ${HW_OUTPUT_FILE} ${CMAKE_CURRENT_SOURCE_DIR}/toolchain/${CORE}.ld
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/toolchain/${CORE}.ld ${DEV_MEM_MAP}
COMMAND ${CMAKE_CXX_COMPILER} -DLD_TARGET=${CORE_DEFINE} -DLD_TYPE=FIRMWARE -I${HW_INCLUDES} -E -P -x c -o ${HW_OUTPUT_FILE} ${CMAKE_CURRENT_SOURCE_DIR}/toolchain/main.ld
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/toolchain/main.ld ${CMAKE_CURRENT_SOURCE_DIR}/toolchain/memory.ld ${CMAKE_CURRENT_SOURCE_DIR}/toolchain/sections.ld ${DEV_MEM_MAP}
COMMENT "Preprocessing toolchain/${CORE}.ld"
VERBATIM
)
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12 changes: 6 additions & 6 deletions tt_metal/hw/firmware/src/brisc.cc
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Expand Up @@ -156,16 +156,16 @@ void set_deassert_addresses() {

#ifdef ARCH_BLACKHOLE
WRITE_REG(RISCV_DEBUG_REG_NCRISC_RESET_PC, MEM_NCRISC_FIRMWARE_BASE);
WRITE_REG(RISCV_DEBUG_REG_TRISC0_RESET_PC, MEM_TRISC0_BASE);
WRITE_REG(RISCV_DEBUG_REG_TRISC1_RESET_PC, MEM_TRISC1_BASE);
WRITE_REG(RISCV_DEBUG_REG_TRISC2_RESET_PC, MEM_TRISC2_BASE);
WRITE_REG(RISCV_DEBUG_REG_TRISC0_RESET_PC, MEM_TRISC0_FIRMWARE_BASE);
WRITE_REG(RISCV_DEBUG_REG_TRISC1_RESET_PC, MEM_TRISC1_FIRMWARE_BASE);
WRITE_REG(RISCV_DEBUG_REG_TRISC2_RESET_PC, MEM_TRISC2_FIRMWARE_BASE);
WRITE_REG(RISCV_DEBUG_REG_TRISC_RESET_PC_OVERRIDE, 0b111);
WRITE_REG(RISCV_DEBUG_REG_NCRISC_RESET_PC_OVERRIDE, 0x1);
#else
cfg_regs[NCRISC_RESET_PC_PC_ADDR32] = MEM_NCRISC_FIRMWARE_BASE;
cfg_regs[TRISC_RESET_PC_SEC0_PC_ADDR32] = MEM_TRISC0_BASE;
cfg_regs[TRISC_RESET_PC_SEC1_PC_ADDR32] = MEM_TRISC1_BASE;
cfg_regs[TRISC_RESET_PC_SEC2_PC_ADDR32] = MEM_TRISC2_BASE;
cfg_regs[TRISC_RESET_PC_SEC0_PC_ADDR32] = MEM_TRISC0_FIRMWARE_BASE;
cfg_regs[TRISC_RESET_PC_SEC1_PC_ADDR32] = MEM_TRISC1_FIRMWARE_BASE;
cfg_regs[TRISC_RESET_PC_SEC2_PC_ADDR32] = MEM_TRISC2_FIRMWARE_BASE;
cfg_regs[TRISC_RESET_PC_OVERRIDE_Reset_PC_Override_en_ADDR32] = 0b111;
cfg_regs[NCRISC_RESET_PC_OVERRIDE_Reset_PC_Override_en_ADDR32] = 0x1;
#endif
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14 changes: 7 additions & 7 deletions tt_metal/hw/inc/blackhole/dev_mem_map.h
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Expand Up @@ -43,9 +43,9 @@
#define MEM_BRISC_FIRMWARE_SIZE (10 * 1024)
#define MEM_NCRISC_FIRMWARE_SIZE (16 * 1024)
#define MEM_IERISC_FIRMWARE_SIZE (16 * 1024)
#define MEM_TRISC0_SIZE (16 * 1024)
#define MEM_TRISC1_SIZE (16 * 1024)
#define MEM_TRISC2_SIZE (16 * 1024)
#define MEM_TRISC0_FIRMWARE_SIZE (16 * 1024)
#define MEM_TRISC1_FIRMWARE_SIZE (16 * 1024)
#define MEM_TRISC2_FIRMWARE_SIZE (16 * 1024)
#define MEM_ZEROS_SIZE 512

#define MEM_BOOT_CODE_BASE 0
Expand All @@ -57,15 +57,15 @@
#define MEM_BRISC_FIRMWARE_BASE (MEM_ZEROS_BASE + MEM_ZEROS_SIZE)
#define MEM_NCRISC_FIRMWARE_BASE (MEM_BRISC_FIRMWARE_BASE + MEM_BRISC_FIRMWARE_SIZE)
#define MEM_IERISC_FIRMWARE_BASE 8192
#define MEM_TRISC0_BASE (MEM_NCRISC_FIRMWARE_BASE + MEM_NCRISC_FIRMWARE_SIZE)
#define MEM_TRISC1_BASE (MEM_TRISC0_BASE + MEM_TRISC0_SIZE)
#define MEM_TRISC2_BASE (MEM_TRISC1_BASE + MEM_TRISC1_SIZE)
#define MEM_TRISC0_FIRMWARE_BASE (MEM_NCRISC_FIRMWARE_BASE + MEM_NCRISC_FIRMWARE_SIZE)
#define MEM_TRISC1_FIRMWARE_BASE (MEM_TRISC0_FIRMWARE_BASE + MEM_TRISC0_FIRMWARE_SIZE)
#define MEM_TRISC2_FIRMWARE_BASE (MEM_TRISC1_FIRMWARE_BASE + MEM_TRISC1_FIRMWARE_SIZE)

/////////////
// Initialization relocation L1 memory
// Host downloads to these addresses, fw copies to destination
// Note: using xmov to copy ncrisc to addresses above 1M hangs the chip
#define MEM_BRISC_INIT_LOCAL_L1_BASE (MEM_TRISC2_BASE + MEM_TRISC2_SIZE)
#define MEM_BRISC_INIT_LOCAL_L1_BASE (MEM_TRISC2_FIRMWARE_BASE + MEM_TRISC2_FIRMWARE_SIZE)
#define MEM_NCRISC_INIT_LOCAL_L1_BASE (MEM_BRISC_INIT_LOCAL_L1_BASE + MEM_BRISC_LOCAL_SIZE)
#define MEM_TRISC0_INIT_LOCAL_L1_BASE (MEM_NCRISC_INIT_LOCAL_L1_BASE + MEM_NCRISC_LOCAL_SIZE)
#define MEM_TRISC1_INIT_LOCAL_L1_BASE (MEM_TRISC0_INIT_LOCAL_L1_BASE + MEM_TRISC_LOCAL_SIZE)
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14 changes: 7 additions & 7 deletions tt_metal/hw/inc/grayskull/dev_mem_map.h
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Expand Up @@ -46,9 +46,9 @@
#define MEM_BRISC_FIRMWARE_SIZE (10 * 1024)
#define MEM_NCRISC_FIRMWARE_SIZE (16 * 1024)
#define MEM_IERISC_FIRMWARE_SIZE (0)
#define MEM_TRISC0_SIZE (16 * 1024)
#define MEM_TRISC1_SIZE (16 * 1024)
#define MEM_TRISC2_SIZE (16 * 1024)
#define MEM_TRISC0_FIRMWARE_SIZE (16 * 1024)
#define MEM_TRISC1_FIRMWARE_SIZE (16 * 1024)
#define MEM_TRISC2_FIRMWARE_SIZE (16 * 1024)
#define MEM_ZEROS_SIZE 512

#define MEM_BOOT_CODE_BASE 0
Expand All @@ -60,9 +60,9 @@
#define MEM_BRISC_FIRMWARE_BASE (MEM_ZEROS_BASE + MEM_ZEROS_SIZE)
#define MEM_NCRISC_FIRMWARE_BASE (MEM_NCRISC_IRAM_BASE)
#define MEM_IERISC_FIRMWARE_BASE 0
#define MEM_TRISC0_BASE (MEM_BRISC_FIRMWARE_BASE + MEM_BRISC_FIRMWARE_SIZE)
#define MEM_TRISC1_BASE (MEM_TRISC0_BASE + MEM_TRISC0_SIZE)
#define MEM_TRISC2_BASE (MEM_TRISC1_BASE + MEM_TRISC1_SIZE)
#define MEM_TRISC0_FIRMWARE_BASE (MEM_BRISC_FIRMWARE_BASE + MEM_BRISC_FIRMWARE_SIZE)
#define MEM_TRISC1_FIRMWARE_BASE (MEM_TRISC0_FIRMWARE_BASE + MEM_TRISC0_FIRMWARE_SIZE)
#define MEM_TRISC2_FIRMWARE_BASE (MEM_TRISC1_FIRMWARE_BASE + MEM_TRISC1_FIRMWARE_SIZE)

// These are used in ncrisc-halt.S, asserted in ncrisc.cc to be valid
// Better way to do this would be to generate a file w/ these addresses
Expand All @@ -72,7 +72,7 @@
/////////////
// Initialization relocation L1 memory
// Host downloads to these addresses, fw copies to destination
#define MEM_BRISC_INIT_LOCAL_L1_BASE (MEM_TRISC2_BASE + MEM_TRISC2_SIZE)
#define MEM_BRISC_INIT_LOCAL_L1_BASE (MEM_TRISC2_FIRMWARE_BASE + MEM_TRISC2_FIRMWARE_SIZE)
#define MEM_NCRISC_INIT_LOCAL_L1_BASE (MEM_BRISC_INIT_LOCAL_L1_BASE + MEM_BRISC_LOCAL_SIZE)
#define MEM_TRISC0_INIT_LOCAL_L1_BASE (MEM_NCRISC_INIT_LOCAL_L1_BASE + MEM_NCRISC_LOCAL_SIZE)
#define MEM_TRISC1_INIT_LOCAL_L1_BASE (MEM_TRISC0_INIT_LOCAL_L1_BASE + MEM_TRISC_LOCAL_SIZE)
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14 changes: 7 additions & 7 deletions tt_metal/hw/inc/wormhole/dev_mem_map.h
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Expand Up @@ -47,9 +47,9 @@
#define MEM_BRISC_FIRMWARE_SIZE (10 * 1024)
#define MEM_NCRISC_FIRMWARE_SIZE (16 * 1024)
#define MEM_IERISC_FIRMWARE_SIZE (16 * 1024)
#define MEM_TRISC0_SIZE (16 * 1024)
#define MEM_TRISC1_SIZE (16 * 1024)
#define MEM_TRISC2_SIZE (16 * 1024)
#define MEM_TRISC0_FIRMWARE_SIZE (16 * 1024)
#define MEM_TRISC1_FIRMWARE_SIZE (16 * 1024)
#define MEM_TRISC2_FIRMWARE_SIZE (16 * 1024)
#define MEM_ZEROS_SIZE 512

#define MEM_BOOT_CODE_BASE 0
Expand All @@ -61,9 +61,9 @@
#define MEM_BRISC_FIRMWARE_BASE (MEM_ZEROS_BASE + MEM_ZEROS_SIZE)
#define MEM_NCRISC_FIRMWARE_BASE (MEM_NCRISC_IRAM_BASE)
#define MEM_IERISC_FIRMWARE_BASE 8192
#define MEM_TRISC0_BASE (MEM_BRISC_FIRMWARE_BASE + MEM_BRISC_FIRMWARE_SIZE)
#define MEM_TRISC1_BASE (MEM_TRISC0_BASE + MEM_TRISC0_SIZE)
#define MEM_TRISC2_BASE (MEM_TRISC1_BASE + MEM_TRISC1_SIZE)
#define MEM_TRISC0_FIRMWARE_BASE (MEM_BRISC_FIRMWARE_BASE + MEM_BRISC_FIRMWARE_SIZE)
#define MEM_TRISC1_FIRMWARE_BASE (MEM_TRISC0_FIRMWARE_BASE + MEM_TRISC0_FIRMWARE_SIZE)
#define MEM_TRISC2_FIRMWARE_BASE (MEM_TRISC1_FIRMWARE_BASE + MEM_TRISC1_FIRMWARE_SIZE)

// These are used in ncrisc-halt.S, asserted in ncrisc.cc to be valid
// Better way to do this would be to generate a file w/ these addresses
Expand All @@ -74,7 +74,7 @@
// Initialization relocation L1 memory
// Host downloads to these addresses, fw copies to destination
// Note: using xmov to copy ncrisc to addresses above 1M hangs the chip
#define MEM_BRISC_INIT_LOCAL_L1_BASE (MEM_TRISC2_BASE + MEM_TRISC2_SIZE)
#define MEM_BRISC_INIT_LOCAL_L1_BASE (MEM_TRISC2_FIRMWARE_BASE + MEM_TRISC2_FIRMWARE_SIZE)
#define MEM_NCRISC_INIT_LOCAL_L1_BASE (MEM_BRISC_INIT_LOCAL_L1_BASE + MEM_BRISC_LOCAL_SIZE)
#define MEM_TRISC0_INIT_LOCAL_L1_BASE (MEM_NCRISC_INIT_LOCAL_L1_BASE + MEM_NCRISC_LOCAL_SIZE)
#define MEM_TRISC1_INIT_LOCAL_L1_BASE (MEM_TRISC0_INIT_LOCAL_L1_BASE + MEM_TRISC_LOCAL_SIZE)
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20 changes: 0 additions & 20 deletions tt_metal/hw/toolchain/BUILD
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18 changes: 0 additions & 18 deletions tt_metal/hw/toolchain/brisc.ld
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6 changes: 0 additions & 6 deletions tt_metal/hw/toolchain/idle-erisc-memory.ld
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