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Assign fixed PCI domain numbers to the host bridge. #124

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Assign fixed PCI domain numbers to the host bridge. #124

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@inindev inindev commented Nov 11, 2023

Without fixed domain numbers, Linux fails to initialize PCI:

pcie-starfive 940000000.pcie: error -ENODEV: failed to get valid pcie domain
pcie-starfive 9c0000000.pcie: error -ENODEV: failed to get valid pcie domain

Fixed PCI domain numbers are found in the upstream patch submission here:
https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/

hal-feng and others added 30 commits September 14, 2023 14:56
@hal-feng
pinctrl: starfive: jh7110: Fix failure to set irq after CONFIG_PM is …
d141aaf 
…enabled

The issue was found when we enabled CONFIG_PM and tested edge events using
libgpiod.

> # gpiomon -r gpiochip0 55
> gpiomon: error waiting for events: Permission denied

`gpiomon` will call irq_chip_pm_get() and then call pm_runtime_resume_and_get()
if (IS_ENABLED(CONFIG_PM) && sfp->gc.irq.domain->pm_dev).
pm_runtime_resume_and_get() will fail if the runtime pm of pinctrl device
is disabled.

As we expect the pinctrl driver can be always working and never suspend
during runtime, unset sfp->gc.irq.domain->pm_dev to make sure
pm_runtime_resume_and_get() won't be called when setting irq.

Fixes: 447976a ("pinctrl: starfive: Add StarFive JH7110 sys controller driver")
Signed-off-by: Hal Feng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
@hal-feng
pinctrl: starfive: jh7110: Add system pm ops to save and restore context
f691a9c 
Add system pm ops to save and restore pinctrl registers
when suspending and resuming the driver, respectively.

Signed-off-by: Hal Feng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
@SFxingyuwu @hal-feng
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
aa9843e 
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.

Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@littleqyp @hal-feng
dt-bindings: soc: starfive: Add StarFive syscon module
46854f1 
Add documentation to describe StarFive System Controller Registers.

Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Co-developed-by: Xingyu Wu <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: William Qiu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@SFxingyuwu @hal-feng
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
f724cac 
Add PLL clock inputs from PLL clock generator.

Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@SFxingyuwu @hal-feng
dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and re…
f4767c5 
…set generator

Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@SFxingyuwu @hal-feng
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock an…
77a0a40 
…d reset generator

Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@SFxingyuwu @hal-feng
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset …
54dac13 
…generator

Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@SFxingyuwu @hal-feng
clk: starfive: Add StarFive JH7110 PLL clock driver
1c25b88 
Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.

Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@SFxingyuwu @hal-feng
clk: starfive: jh7110-sys: Add PLL clocks source from DTS
c671f4f 
Modify PLL clocks source to be got from DTS or
the fixed factor clocks.

Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@esmil @hal-feng
clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
8c8dc30 
Add driver for the StarFive JH7110 System-Top-Group clock controller.

Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
Co-developed-by: Xingyu Wu <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@SFxingyuwu @hal-feng
clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
a9689d9 
Add driver for the StarFive JH7110 Image-Signal-Process clock controller.
And these clock controllers should power on and enable the clocks from
SYSCRG before registering.

Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@SFxingyuwu @hal-feng
clk: starfive: Add StarFive JH7110 Video-Output clock driver
52f4ed0 
Add driver for the StarFive JH7110 Video-Output clock controller.
And these clock controllers should power on and enable the clocks from
SYSCRG first before registering.

Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@SFxingyuwu @hal-feng
reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support
108c23b 
Add new struct members and auxiliary_device_id of resets to support
System-Top-Group, Image-Signal-Process and Video-Output on the StarFive
JH7110 SoC.

Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
@SFxingyuwu @hal-feng
clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by setting PLL0 …
88a95b7 
…rate to 1.5GHz

CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
333/500/500/1000MHz in fact.

So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock
and the divider of cpu_core before the setting.

Reviewed-by: Hal Feng <[email protected]>
Fixes: e2c510d ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <[email protected]>
@pcercuei @hal-feng
watchdog: starfive: Remove #ifdef guards for PM related functions
1848389 
Use the new PM macros for the suspend and resume functions to be
automatically dropped by the compiler when CONFIG_PM or
CONFIG_PM_SLEEP are disabled, without having to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
@SFxingyuwu @hal-feng
dt-bindings: timer: Add timer for StarFive JH7110 SoC
3db9a11 
Add bindings for the timer on the JH7110 RISC-V SoC
by StarFive Technology Ltd.

Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
@SFxingyuwu @hal-feng
clocksource: Add JH7110 timer driver
895975d 
Add timer driver for the StarFive JH7110 SoC.

Signed-off-by: Xingyu Wu <[email protected]>
@SaminGuo @hal-feng
dt-bindings: net: motorcomm: Add pad driver strength cfg
4c1d138 
The motorcomm phy (YT8531) supports the ability to adjust the drive
strength of the rx_clk/rx_data.

The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the
LDO voltage can be configured with hardware pull-up resistors to match
the SOC voltage (usually 1.8V). The software can read the registers
0xA001 obtain the current LDO voltage value.

Reviewed-by: Hal Feng <[email protected]>
Signed-off-by: Samin Guo <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
@SaminGuo @hal-feng
net: phy: motorcomm: Add pad drive strength cfg support
17db06c 
The motorcomm phy (YT8531) supports the ability to adjust the drive
strength of the rx_clk/rx_data, and the default strength may not be
suitable for all boards. So add configurable options to better match
the boards.(e.g. StarFive VisionFive 2)

When we configure the drive strength, we need to read the current
LDO voltage value to ensure that it is a legal value at that LDO
voltage.

Reviewed-by: Hal Feng <[email protected]>
Signed-off-by: Samin Guo <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
@littleqyp @hal-feng
dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
77fbacf 
The QSPI controller needs three clock items to work properly on StarFive
JH7110 SoC, so there is need to change the maxItems's value to 3.

Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
@littleqyp @hal-feng
spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI
46e228b 
Add JH7110's clock initialization code to the driver.

Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
@littleqyp @hal-feng
dt-bindings: pwm: Add StarFive PWM module
0c2db63 
Add documentation to describe StarFive Pulse Width Modulation
controller driver.

Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
@littleqyp @hal-feng
pwm: starfive: Add PWM driver support
fb841ea 
Add Pulse Width Modulation driver support for StarFive
JH7100 and JH7110 SoC.

Co-developed-by: Hal Feng <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
Signed-off-by: William Qiu <[email protected]>
@littleqyp @hal-feng
dt-bindings: spi: add reference file to YAML
09cd548 
In JH7110 SoC, the spi module needs to use "arm,primecell-periphid" to
override the h/w ID value to  correctly init "spi_dev", so add
"primecell.yaml" as the reference file for YAML.

Signed-off-by: William Qiu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
@jiajieho @hal-feng
riscv: Kconfig: Add select ARM_AMBA to SOC_STARFIVE
5856d83 
Selects ARM_AMBA platform support for StarFive SoCs required by spi and
crypto dma engine.

Signed-off-by: Jia Jie Ho <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@hal-feng
crypto: starfive - Convert to platform remove callback returning void
7bcf8ed 
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new() which already returns void. Eventually after all drivers
are converted, .remove_new() is renamed to .remove().

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
@jiajieho @hal-feng
crypto: starfive - Add AES skcipher and aead support
c30d686 
Adding AES skcipher and aead support to Starfive crypto module.
Skcipher modes of operation include ecb, cbc, ctr, ofb, cfb. Aead modes
include ccm and gcm.

v1->v2:
- Add include interrupt.h to fix compile error. (Herbert)

Co-developed-by: Huan Feng <[email protected]>
Signed-off-by: Huan Feng <[email protected]>
Signed-off-by: Jia Jie Ho <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
@hal-feng
crypto: starfive - fix return value check in starfive_aes_prepare_req()
e8427a1 
kzalloc() returns NULL pointer not PTR_ERR() when it fails,
so replace the IS_ERR() check with NULL pointer check.

Fixes: e22471c ("crypto: starfive - Add AES skcipher and aead support")
Signed-off-by: Yang Yingliang <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
@mindachen1987 @hal-feng
dt-bindings: phy: Add StarFive JH7110 USB PHY
fa2a510 
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.

Signed-off-by: Minda Chen <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
jackzhustf and others added 22 commits September 14, 2023 14:58
@jackzhustf @hal-feng
media: cadence: Add operation on reset
858ff55 
Add operation on reset for Cadence MIPI-CSI2 RX Controller.

Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Jack Zhu <[email protected]>
Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
@jackzhustf @hal-feng
media: cadence: Add support for external dphy
b4dc0dc 
Add support for external MIPI D-PHY.

Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Jack Zhu <[email protected]>
Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
@jackzhustf @hal-feng
media: cadence: Add support for JH7110 SoC
e353ca7 
Add support for Starfive JH7110 SoC which has the cadence csi2 receiver.

Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Jack Zhu <[email protected]>
Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
@jackzhustf @hal-feng
media: dt-bindings: Add JH7110 Camera Subsystem
bb10c54 
Add the bindings documentation for Starfive JH7110 Camera Subsystem
which is used for handing image sensor data.

Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Jack Zhu <[email protected]>
@jackzhustf @hal-feng
media: admin-guide: Add starfive_camss.rst for Starfive Camera Subsystem
b918d5f 
Add starfive_camss.rst file that documents the Starfive Camera
Subsystem driver which is used for handing image sensor data.

Signed-off-by: Jack Zhu <[email protected]>
@jackzhustf @hal-feng
media: staging: media: starfive: camss: Add core driver
1ace0ff 
Add core driver for StarFive Camera Subsystem. The code parses
the device platform resources and registers related devices.

Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Jack Zhu <[email protected]>
@jackzhustf @hal-feng
media: staging: media: starfive: camss: Add video driver
6cca95e 
Add video driver for StarFive Camera Subsystem.

Signed-off-by: Jack Zhu <[email protected]>
@jackzhustf @hal-feng
media: staging: media: starfive: camss: Add ISP driver
6c9e274 
Add ISP driver for StarFive Camera Subsystem.

Signed-off-by: Jack Zhu <[email protected]>
@jackzhustf @hal-feng
media: staging: media: starfive: camss: Add capture driver
72abbe9 
Add capture driver for StarFive Camera Subsystem. It contains two video
devices: capture_yuv and capture_raw.

Signed-off-by: Jack Zhu <[email protected]>
@jackzhustf @hal-feng
media: staging: media: starfive: camss: Add interrupt handling
3a39213 
Parse interrupt resources and register interrupt handlers.

Signed-off-by: Jack Zhu <[email protected]>
@jackzhustf @hal-feng
media: staging: media: starfive: camss: Register devices
e223b1e 
Register ISP sub-device and video devices for StarFive Camera
Subsystem.

Signed-off-by: Jack Zhu <[email protected]>
@kJugg @hal-feng
dt-bindings: display: Add yamls for JH7110 display system
d883b40 
StarFive SoCs JH7110 display system:
lcd-controller bases verisilicon dc8200 IP,
and hdmi bases Innosilicon IP.
Add bindings for them.

Signed-off-by: Keith Zhao <[email protected]>
@kJugg @hal-feng
drm/fourcc: Add drm/vs tiled modifiers
9f257a7 
These are mainly used internally in vs-drm,
I'm not sure if the new modifiers can be used with the existing ones.
If there is a problem, I will improve it further.

Signed-off-by: Keith Zhao <[email protected]>
@kJugg @hal-feng
drm/vs: Register DRM device
4af2e5f 
Implement drm device registration interface

Signed-off-by: Keith Zhao <[email protected]>
@kJugg @hal-feng
drm/vs: Add KMS crtc&plane
4dd0e97 
add 2 crtcs and 8 planes in vs-drm

Signed-off-by: Keith Zhao <[email protected]>
@kJugg @hal-feng
drm/vs: Add hdmi
bafa580 
add hdmi driver as encoder and connect

Signed-off-by: Keith Zhao <[email protected]>
@fmoessbauer @hal-feng
riscv: dts: Enable device-tree overlay support for starfive devices
003a1ee 
Add the '-@' DTC option for the starfive devices. This option
populates the '__symbols__' node that contains all the necessary symbols
for supporting device-tree overlays (for instance from the firmware or
the bootloader) on these devices.

The starfive devices allow various modules to be connected and this
enables users to create out-of-tree device-tree overlays for these modules.

Please note that this change does increase the size of the resulting DTB
by ~20%. For example, with v6.4 increase in size is as follows:

jh7100-beaglev-starlight.dtb 6192 -> 7339
jh7100-starfive-visionfive-v1.dtb 6281 -> 7428
jh7110-starfive-visionfive-2-v1.2a.dtb 11101 -> 13447
jh7110-starfive-visionfive-2-v1.3b.dtb 11101 -> 13447

Signed-off-by: Felix Moessbauer <[email protected]>
Acked-by: Emil Renner Berthing <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
@hal-feng
riscv: dts: starfive: Add full support for JH7110 and VisionFive 2 board
48aa08b 
Merge all StarFive dts patches together.

Signed-off-by: Hal Feng <[email protected]>
@hal-feng
MAINTAINERS: Update all StarFive entries
596ab26 
Merge all StarFive maintainers changes together.

Signed-off-by: Hal Feng <[email protected]>
@hal-feng
[NOT-FOR-UPSTREAM] Add starfive_visionfive2_defconfig for test
20ab944 
Signed-off-by: Hal Feng <[email protected]>
@hal-feng
[NOT-FOR-UPSTREAM] Add readme
73a14d3 
Signed-off-by: Hal Feng <[email protected]>
@inindev
Assign fixed PCI domain numbers to the host bridge.
bdb039e 
Without fixed domain numbers, Linux fails to initialize PCI:

pcie-starfive 940000000.pcie: error -ENODEV: failed to get valid pcie domain
pcie-starfive 9c0000000.pcie: error -ENODEV: failed to get valid pcie domain

Signed-off-by: John Clark <[email protected]>
@hal-feng hal-feng force-pushed the JH7110_VisionFive2_upstream branch 2 times, most recently from 7ccbe46 to 9fe004e Compare November 21, 2023 02:59
@hal-feng hal-feng force-pushed the JH7110_VisionFive2_upstream branch 5 times, most recently from 2b4dfa3 to 13eb70d Compare January 18, 2024 10:50
@hal-feng hal-feng force-pushed the JH7110_VisionFive2_upstream branch from 13eb70d to 076ede0 Compare January 30, 2024 08:39
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