sg200x: trm: update text for reset

SG200X/TRM/contents/cn/reset/reset_control.rst

@@ -1,51 +1,32 @@
 复位控制
 --------
 
+芯片内部存在三个层级的复位管理模块对整个芯片、子系统，各个功能模块的复位进行管理。
+
 .. _diagram_reset_block:
 .. figure:: ../../../../media/image6.png
 	:align: center
 
 	复位管理模块框图
 
-上电复位
-~~~~~~~~
-
-上电复位 (POR) 由实时时钟模块配合全局电源管理与晶振时序生成。详情参照章节 :ref:`section_rtc`。
-
-系统硬复位
-~~~~~~~~~~
-
-系统硬复位 (System Hard Reset) 由 Reset Ctrl Level2 生成，对芯片全局包含子系统及各功能模块进行硬复位，来源由以下途径：
+Reset Ctrl Level 1 电路负责系统上电复位功能。上电复位 (POR) 由实时时钟模块配合全局电源管理与晶振时序生成。详情参照章节 :ref:`section_rtc`。来源由以下途径：
 
 -  上电复位
 
--  看门狗复位
-
 -  过热保护复位
 
--  外部复位管脚 (RSTN)
+-  看门狗复位。RCT_CTRL0.hw_wdg_rst_en 为 1, (见 :ref:`table_rtc_ctrl0`) 且 sys_ctrl_reg.reg_sw_root_reset_en 的 bit[0] 为 0 (见 :ref:`table_sys_ctrl_reg`) 情况下 Watchdog 定时器超时触发系统复位。
 
-   -  内建去抖动电路，RSTN 高低电平有效信号须达 6.56ms。
+Reset Ctrl Level 2 电路负责产生系统硬复位 (System Hard Reset)，对芯片全局包含子系统及各功能模块进行硬复位，来源由以下途径：
 
-软复位
-~~~~~~
+-  看门狗复位, sys_ctrl_reg.reg_sw_root_reset_en 的 bit[0] 为 1 (见 :ref:`table_sys_ctrl_reg`) 情况下 Watchdog 定时器超时触发系统复位。
 
-软复位控制通过配置相应的复位配置寄存器 (Reset CRG)，由 Reset Ctrl Level3实现，包含：
+-  外部复位管脚 (RSTN)，内建去抖动电路 (Debounce), RSTN 高低电平有效信号须达 6.56ms。
 
--  系统软复位 : 复位全芯片，除少部分电路及 RTC 内部电路。
+Reset Ctrl Level 3 电路负责提供实现软复位控制相应的复位配置寄存器 (Reset CRG)，具体参考 :ref:`section_reset_configure_registers`。包含：
 
--  处理器子系统复位 : 复位处理器及处理器子系统。
-
--  功能子系统复位 : 复位各功能子系统及功能模块。
-
--  功能模块复位 : 复位各功能模块。
-
-处理器子系统软复位
-~~~~~~~~~~~~~~~~~~
-
-操作寄存器 SOFT_AC_RSTN_0 可对处理器及子系统做软复位，配置寄存器写 0 后，复位控制器会等待 24us 延时后才触发相应处理器复位。这段期间处理器应结束对总线之访问，以避免复位后总线挂死。触发复位后对应之复位信号会持续 8us 后自动解除，处理器及处理器子系统完成复位并开始启动。
+-  系统软复位 : 复位全芯片，除少部分电路及 RTC 内部电路。
 
-功能子系统及功能模块软复位
-~~~~~~~~~~~~~~~~~~~~~~~~~~
+-  处理器子系统复位 : 复位处理器及处理器子系统。操作寄存器 SOFT_CPUAC_RSTN 可对处理器及子系统做软复位，配置寄存器写 0 后，复位控制器会等待 24us 延时后才触发相应处理器复位。这段期间处理器应结束对总线之访问，以避免复位后总线挂死。触发复位后对应之复位信号会持续 8us 后自动解除，处理器及处理器子系统完成复位并开始启动。
 
-操作寄存器 SOFT_RSTN_0 ~ 3，可对各功能模块进行软复位。复位配置为低电平有效，复位信号并不会自动清除，故软件配置相应寄存器为 0 触发复位后，亦需配置为 1 解除复位。复位前须确保各功能模块及功能子系统内置 DMA 对总线访问与处理器对模块之访问处于闲置状态。否则将使复位失败易造成系统挂死。
+-  功能子系统及功能模块复位: 复位各功能子系统及功能模块。操作寄存器 SOFT_RSTN_0 ~ 3，可对各功能模块进行软复位。复位配置为低电平有效，复位信号并不会自动清除，故软件配置相应寄存器为 0 触发复位后，亦需配置为 1 解除复位。复位前须确保各功能模块及功能子系统内置 DMA 对总线访问与处理器对模块之访问处于闲置状态。否则将使复位失败易造成系统挂死。

SG200X/TRM/contents/cn/reset/reset_registers.rst

@@ -1,3 +1,5 @@
+.. _section_reset_configure_registers:
+
 复位配置寄存器 
 --------------
 

SG200X/TRM/contents/en/reset/reset_control.rst

@@ -1,51 +1,32 @@
 Reset Control
 -------------
 
+There are three levels of reset management modules inside the chip to manage the reset of the entire chip, subsystems, and various functional modules.
+
 .. _diagram_reset_block:
 .. figure:: ../../../../media/image6.png
 	:align: center
 
 	Reset management module block diagram
 
-Power On Reset
-~~~~~~~~~~~~~~
-
-A Power-On-Reset (POR) is generated by the real-time clock module in conjunction with global power management and crystal timing. See section :ref:`section_rtc` for details.
-
-System Hard Reset
-~~~~~~~~~~~~~~~~~
-
-System Hard Reset is generated by Reset Ctrl Level2. It performs a hard reset on the global chip including subsystems and functional modules. The source is from the following channels:
+The Reset Ctrl Level 1 circuit is responsible for the system power-on reset function. The power-on reset (POR) is generated by the real-time clock module in conjunction with the global power management and crystal timing. For details, refer to the section :ref:`section_rtc`. Level 1 Reset can be triggered in the following ways:
 
 - Power on reset
 
-- Watchdog reset
-
 - Overheat protection reset
 
-- External reset pin (RSTN)
+- Watchdog reset: When RCT_CTRL0.hw_wdg_rst_en is 1 (see :ref:`table_rtc_ctrl0`) and bit[0] of sys_ctrl_reg.reg_sw_root_reset_en is 0 (see :ref:`table_sys_ctrl_reg`), the watchdog timer times out and triggers a system reset.
 
-    - Built-in debounce circuit, RSTN high and low level effective signals must reach 6.56ms.
+The Reset Ctrl Level 2 circuit is responsible for generating a System Hard Reset, which performs a hard reset on the chip globally including subsystems and functional modules. Level 2 Reset can be triggered in the following ways:
 
-Soft Reset
-~~~~~~~~~~
+- Watchdog reset: When bit[0] of sys_ctrl_reg.reg_sw_root_reset_en is 1 (see :ref:`table_sys_ctrl_reg`), the watchdog timer times out and triggers a system reset.
 
-Soft Reset control is implemented by Reset Ctrl Level3 by configuring the corresponding reset configuration register (Reset CRG), including:
+- External reset pin (RSTN), which has beuilt-in debounce circuit, RSTN high and low level effective signals must reach 6.56ms.
 
-- System soft reset: Reset the entire chip, except for a few circuits and RTC internal circuits.
+The Reset Ctrl Level 3 circuit is responsible for providing the reset configuration register (Reset CRG) corresponding to the soft reset control. For details, refer to :ref:`section_reset_configure_registers`. It includes:
 
-- Processor subsystem reset: Resets the processor and processor subsystem.
-
-- Functional subsystem reset: Reset each functional subsystem and functional modules.
-
-- Function module reset: Reset each function module.
-
-Processor subsystem soft reset
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Programming of register SOFT_AC_RSTN_0 can soft reset the processor and subsystem. After writing 0 to the configuration register, the reset controller will wait for a 24us delay before triggering the corresponding processor reset. During this period, the processor should end access to the bus to avoid the bus hanging after reset. After triggering the reset, the corresponding reset signal will last for 8us and then be automatically released. The processor and processor subsystem will complete the reset and start booting.
+- System soft reset: Reset the entire chip, except for a few circuits and RTC internal circuits.
 
-Soft reset of functional subsystems and functional modules
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+- Processor subsystem reset: Resets the processor and processor subsystem. Programming of register SOFT_CPUAC_RSTN can soft reset the processor and subsystem. After writing 0 to the configuration register, the reset controller will wait for a 24us delay before triggering the corresponding processor reset. During this period, the processor should end access to the bus to avoid the bus hanging after reset. After triggering the reset, the corresponding reset signal will last for 8us and then be automatically released. The processor and processor subsystem will complete the reset and start booting.
 
-Programming of register SOFT_RSTN_0 ~ 3 can soft reset each functional module. The reset configuration is active low, and the reset signal will not be cleared automatically. Therefore, after the software configures the corresponding register to 0 to trigger the reset, it also needs to be configured to 1 to release the reset. Before resetting, make sure that the built-in DMA of each functional module and functional subsystem to the bus and the processor to the module are idle. Otherwise, the reset will fail and the system may hang.
+- Functional subsystem and modules reset: Reset each functional subsystem and functional modules. Programming of register SOFT_RSTN_0 ~ 3 can soft reset each functional module. The reset configuration is active low, and the reset signal will not be cleared automatically. Therefore, after the software configures the corresponding register to 0 to trigger the reset, it also needs to be configured to 1 to release the reset. Before resetting, make sure that the built-in DMA of each functional module and functional subsystem to the bus and the processor to the module are idle. Otherwise, the reset will fail and the system may hang.

SG200X/TRM/contents/en/reset/reset_registers.rst

@@ -1,3 +1,5 @@
+.. _section_reset_configure_registers:
+
 Reset configuration register
 ----------------------------