sg200x:trm: add two timer init value description for watchdog

Signed-off-by: Chen Wang <[email protected]>
sophgo · Jun 16, 2024 · 1e68006 · 1e68006
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diff --git a/SG200X/TRM/contents/cn/watchdog/functionalities.rst b/SG200X/TRM/contents/cn/watchdog/functionalities.rst
@@ -14,11 +14,8 @@
 功能原理
 ~~~~~~~~
 
-WatchDog 的计数初值由寄存器 WDT_TORR 载入，运行基于 1个 32bit 减法计数器。
+WatchDog 运行基于 1个 32bit 减法计数器。其计数初值有两个来源，分别从 WDT_ITORR 和 WDT_TORR 载入，并依据 ITOR_MODE 的值计算得到（具体计算方法参考 :ref:`table_wdt_torr` 中的描述）。WDT_ITORR 用于上电后 WatchDog 的第一次定时器计数，其后的定时器计数基于 WDT_TORR 得到。
 
 在 WatchDog 时钟使能情况下，计数值在每个计数时钟的上升沿减 1。当计数值递减到 0, WatchDog 将产生一个中断。然后在下一个计数时钟上升沿，计数器又从寄存器 WDT_TORR 中重新载入计数初值，开始递减计数。
 
-如果计数器的计数值第二次计数递减到 0 时, CPU还没有清除 WatchDog 中断，则 WatchDog 将发出复位信号WDT_SYS_RST, 计数器停止计数。
-
-用户可以通过设置寄存器 WDT_CR[1] 决定是否在计数器的计数值第一次计数递减到 0 时立刻发出复位信号 WDT_SYS_RST。
-
+用户可以通过设置寄存器 WDT_CR[1] 决定是否在计数器的计数值第一次计数递减到 0 时立刻发出复位信号 WDT_SYS_RST，如果设置为 0 则立即发出复位信号，否则如果为 1 则产生一个中断，并开始第二次计数，如果第二次计数递减到 0 时, CPU 还没有清除 WatchDog 中断，则 WatchDog 将发出复位信号 WDT_SYS_RST, 计数器停止计数。
diff --git a/SG200X/TRM/contents/en/watchdog/functionalities.rst b/SG200X/TRM/contents/en/watchdog/functionalities.rst
@@ -14,10 +14,8 @@ Application Block Diagram
 Functional Principle
 ~~~~~~~~~~~~~~~~~~~~
 
-The initial counting value of WatchDog is loaded from the register WDT_TORR, and the operation is based on a 32-bit subtraction counter.
+WatchDog runs based on a 32-bit down counter. Its initial count value has two sources, loaded from WDT_ITORR and WDT_TORR respectively, and calculated based on the value of ITOR_MODE (for specific calculation methods, refer to the description in :ref:`table_wdt_torr`). WDT_ITORR is used for the first timer count of WatchDog after power-on, and subsequent timer counts are based on WDT_TORR.
 
 When the WatchDog clock is enabled, the count value is decremented by 1 on the rising edge of each count clock. When the count value decreases to 0, WatchDog will generate an interrupt. Then at the next rising edge of the counting clock, the counter reloads the initial counting value from the register WDT_TORR and starts counting down.
 
-If the count value of the counter decreases to 0 for the second time and the CPU has not cleared the WatchDog interrupt, WatchDog will issue a reset signal WDT_SYS_RST and the counter will stop counting.
-
-The user can decide whether to send the reset signal WDT_SYS_RST immediately when the counter's count value decreases to 0 for the first time by setting the register WDT_CR[1].
+The user can set the register WDT_CR[1] to decide whether to send a reset signal WDT_SYS_RST immediately when the counter count value decreases to 0 for the first time. If it is set to 0, a reset signal is sent immediately. Otherwise, if it is 1, an interrupt is generated and the second count starts. If the CPU has not cleared the WatchDog interrupt when the second count decreases to 0, WatchDog will send a reset signal WDT_SYS_RST and the counter will stop counting.