[*] Add .read() operation for an input and signals variables in syste…

…mc (rtlgen update)
sergeykhbr · Dec 15, 2023 · a3589d9 · a3589d9
1 parent 434a100
commit a3589d9
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Showing 13 changed files with 27 additions and 27 deletions.
diff --git a/sc/rtl/misclib/apb_prci.cpp b/sc/rtl/misclib/apb_prci.cpp
@@ -120,8 +120,8 @@ void apb_prci::comb() {
 
     v = r;
 
-    v.sys_rst = (i_pwrreset || (!i_sys_locked.read()) || i_dmireset);
-    v.sys_nrst = (!(i_pwrreset || (!i_sys_locked.read()) || i_dmireset));
+    v.sys_rst = (i_pwrreset.read() || (!i_sys_locked.read()) || i_dmireset.read());
+    v.sys_nrst = (!(i_pwrreset.read() || (!i_sys_locked.read()) || i_dmireset.read()));
     v.dbg_nrst = (!(i_pwrreset.read() || (!i_sys_locked.read())));
 
     // Registers access:

diff --git a/sc/rtl/riverlib/cache/dcache_lru.cpp b/sc/rtl/riverlib/cache/dcache_lru.cpp
@@ -688,8 +688,8 @@ void DCacheLru::comb() {
             || (coherence_ena_ && v_ready_next && i_req_snoop_type.read().or_reduce())
             || v_req_snoop_ready_on_wait);
 
-    v.snoop_flags_valid = (i_req_snoop_valid
-            && line_snoop_ready_o
+    v.snoop_flags_valid = (i_req_snoop_valid.read()
+            && line_snoop_ready_o.read()
             && (!i_req_snoop_type.read().or_reduce()));
 
     if (v_ready_next == 1) {

diff --git a/sc/rtl/riverlib/cache/lrunway.h b/sc/rtl/riverlib/cache/lrunway.h
@@ -112,7 +112,7 @@ void lrunway<abits, waybits>::comb() {
     v.radr = i_raddr;
     wb_tbl_rdata = r.mem[r.radr.read().to_int()];
 
-    v_we = (i_up || i_down || i_init);
+    v_we = (i_up.read() || i_down.read() || i_init.read());
 
     // init table value
     for (int i = 0; i < WAYS_TOTAL; i++) {

diff --git a/sc/rtl/riverlib/core/bp.cpp b/sc/rtl/riverlib/core/bp.cpp
@@ -205,7 +205,7 @@ void BranchPredictor::comb() {
         }
     }
 
-    v_btb_we = (i_e_jmp || wb_pd[0].jmp || wb_pd[1].jmp);
+    v_btb_we = (i_e_jmp.read() || wb_pd[0].jmp || wb_pd[1].jmp);
     if (i_e_jmp.read() == 1) {
         vb_btb_we_pc = i_e_pc;
         vb_btb_we_npc = i_e_npc;

diff --git a/sc/rtl/riverlib/core/bp_predec.cpp b/sc/rtl/riverlib/core/bp_predec.cpp
@@ -153,7 +153,7 @@ void BpPreDecoder::comb() {
         vb_npc = (vb_pc + 4);
     }
 
-    o_jmp = (v_jal || v_branch || v_c_j || v_c_ret);
+    o_jmp = (v_jal.read() || v_branch.read() || v_c_j.read() || v_c_ret.read());
     o_pc = vb_pc;
     o_npc = vb_npc;
 }

diff --git a/sc/rtl/riverlib/core/execute.cpp b/sc/rtl/riverlib/core/execute.cpp
@@ -987,18 +987,18 @@ void InstrExecute::comb() {
         v_ret = 1;
     }
 
-    v_mem_ex = (r.mem_ex_load_fault
-            || r.mem_ex_store_fault
-            || i_page_fault_x
-            || r.page_fault_r
-            || r.page_fault_w);
-    v_csr_cmd_ena = (i_haltreq
+    v_mem_ex = (r.mem_ex_load_fault.read()
+            || r.mem_ex_store_fault.read()
+            || i_page_fault_x.read()
+            || r.page_fault_r.read()
+            || r.page_fault_w.read());
+    v_csr_cmd_ena = (i_haltreq.read()
             || (i_step.read() && r.stepdone.read())
-            || i_unsup_exception
-            || i_instr_load_fault
+            || i_unsup_exception.read()
+            || i_instr_load_fault.read()
             || v_mem_ex
-            || r.stack_overflow
-            || r.stack_underflow
+            || r.stack_overflow.read()
+            || r.stack_underflow.read()
             || v_instr_misaligned
             || v_load_misaligned
             || v_store_misaligned

diff --git a/sc/rtl/riverlib/core/fpu_d/fadd_d.cpp b/sc/rtl/riverlib/core/fpu_d/fadd_d.cpp
@@ -257,7 +257,7 @@ void DoubleAdd::comb() {
         v.overflow = 0;
     }
 
-    signOp = (r.sub || r.le || r.lt);
+    signOp = (r.sub.read() || r.le.read() || r.lt.read());
     signA = r.a.read()[63];
     signB = r.b.read()[63];
     signOpB = (signB ^ signOp);

diff --git a/sc/rtl/riverlib/core/fpu_d/fdiv_d.cpp b/sc/rtl/riverlib/core/fpu_d/fdiv_d.cpp
@@ -365,8 +365,8 @@ void DoubleDiv::comb() {
     } else if ((nanB && (!mantZeroB)) == 1) {
         res[51] = 1;
         res(50, 0) = r.b.read()(50, 0);
-    } else if ((r.overflow
-                || r.nanRes
+    } else if ((r.overflow.read()
+                || r.nanRes.read()
                 || (nanA && mantZeroA)
                 || (nanB && mantZeroB)) == 1) {
         res(51, 0) = 0;

diff --git a/sc/rtl/riverlib/core/fpu_d/fmul_d.cpp b/sc/rtl/riverlib/core/fpu_d/fmul_d.cpp
@@ -326,7 +326,7 @@ void DoubleMul::comb() {
     }
 
     // Result multiplexers:
-    if ((nanA && mantZeroA && r.zeroB) || (nanB && mantZeroB && r.zeroA)) {
+    if ((nanA && mantZeroA && r.zeroB.read()) || (nanB && mantZeroB && r.zeroA.read())) {
         v_res_sign = 1;
     } else if ((nanA && (!mantZeroA)) == 1) {
         // when both values are NaN, value B has higher priority if sign=1
@@ -341,7 +341,7 @@ void DoubleMul::comb() {
         vb_res_exp = r.a.read()(62, 52);
     } else if (nanB == 1) {
         vb_res_exp = r.b.read()(62, 52);
-    } else if ((r.expAlign.read()[11] || r.zeroA || r.zeroB) == 1) {
+    } else if ((r.expAlign.read()[11] || r.zeroA.read() || r.zeroB.read()) == 1) {
         vb_res_exp = 0;
     } else if (r.overflow.read() == 1) {
         vb_res_exp = ~0ull;
@@ -352,7 +352,7 @@ void DoubleMul::comb() {
 
     if ((nanA && mantZeroA && (!mantZeroB))
             || (nanB && mantZeroB && (!mantZeroA))
-            || ((!nanA) && (!nanB) && r.overflow)) {
+            || ((!nanA) && (!nanB) && r.overflow.read())) {
         vb_res_mant = 0;
     } else if ((nanA && (!(nanB && signB))) == 1) {
         // when both values are NaN, value B has higher priority if sign=1

diff --git a/sc/rtl/riverlib/core/memaccess.cpp b/sc/rtl/riverlib/core/memaccess.cpp
@@ -620,7 +620,7 @@ void MemAccess::comb() {
     }
 
     queue_re = v_queue_re;
-    o_flushd = (queue_nempty && v_flushd && v_queue_re);
+    o_flushd = (queue_nempty.read() && v_flushd && v_queue_re);
     o_mmu_ena = v_mmu_ena;
     o_mmu_sv39 = v_mmu_sv39;
     o_mmu_sv48 = v_mmu_sv48;

diff --git a/sc/rtl/riverlib/core/mmu.cpp b/sc/rtl/riverlib/core/mmu.cpp
@@ -567,7 +567,7 @@ void Mmu::comb() {
             v.resp_data = i_mem_resp_data;
             v.resp_load_fault = i_mem_resp_load_fault;      // Hardware error Load (unmapped access)
             v.resp_store_fault = i_mem_resp_store_fault;    // Hardware error Store/AMO (unmapped access)
-            if ((r.tlb_hit || i_mem_resp_load_fault || i_mem_resp_store_fault) == 1) {
+            if ((r.tlb_hit.read() || i_mem_resp_load_fault.read() || i_mem_resp_store_fault.read()) == 1) {
                 v.state = AcceptCore;
             } else {
                 v.state = HandleResp;

diff --git a/sc/rtl/riverlib/core/regibank.cpp b/sc/rtl/riverlib/core/regibank.cpp
@@ -207,7 +207,7 @@ void RegIntBank::comb() {
         }
     }
 
-    o_ignored = (i_wena && i_waddr.read().or_reduce() && i_inorder && (!v_inordered));
+    o_ignored = (i_wena.read() && i_waddr.read().or_reduce() && i_inorder.read() && (!v_inordered));
     o_rdata1 = r.arr[int_radr1].val;
     o_rtag1 = r.arr[int_radr1].tag;
     o_rdata2 = r.arr[int_radr2].val;

diff --git a/sc/rtl/riverlib/dmi/jtagcdc.cpp b/sc/rtl/riverlib/dmi/jtagcdc.cpp
@@ -111,7 +111,7 @@ void jtagcdc::comb() {
     } else if (i_dmi_req_ready.read() == 1) {
         v.req_valid = 0;
     }
-    if ((r.l2.read()[0] && r.req_valid && i_dmi_req_ready) == 1) {
+    if ((r.l2.read()[0] && r.req_valid.read() && i_dmi_req_ready.read()) == 1) {
         v.req_accepted = 1;
     } else if (r.l2.read()[0] == 0) {
         v.req_accepted = 0;