[*] rtlgen updates: dependency file tracker was modified, so include …

…list changed in systemc
sergeykhbr · Dec 3, 2023 · 9c78886 · 9c78886
1 parent df39bbe
commit 9c78886
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Showing 9 changed files with 1 addition and 16 deletions.
diff --git a/sc/prj/impl/asic/asic_top.h b/sc/prj/impl/asic/asic_top.h
@@ -18,12 +18,6 @@
 #include <systemc.h>
 #include "../../../rtl/ambalib/types_amba.h"
 #include "../../../rtl/ambalib/types_pnp.h"
-#include "../../../rtl/ambalib/types_bus0.h"
-#include "../../../rtl/ambalib/types_bus1.h"
-#include "../../../rtl/riverlib/river_cfg.h"
-#include "../../../rtl/riverlib/types_river.h"
-#include "../../../rtl/sdctrl/sdctrl_cfg.h"
-#include "target_cfg.h"
 #include "../../../rtl/techmap/bufg/ids_tech.h"
 #include "../../../rtl/techmap/bufg/iobuf_tech.h"
 #include "../../../rtl/techmap/pll/SysPLL_tech.h"

diff --git a/sc/rtl/riscv_soc.h b/sc/rtl/riscv_soc.h
@@ -21,9 +21,6 @@
 #include "ambalib/types_bus0.h"
 #include "ambalib/types_bus1.h"
 #include "riverlib/river_cfg.h"
-#include "riverlib/types_river.h"
-#include "sdctrl/sdctrl_cfg.h"
-#include "../prj/impl/asic/target_cfg.h"
 #include "ambalib/axictrl_bus0.h"
 #include "ambalib/axi2apb_bus1.h"
 #include "misclib/axi_rom.h"

diff --git a/sc/rtl/riverlib/cache/cache_top.h b/sc/rtl/riverlib/cache/cache_top.h
@@ -17,7 +17,6 @@
 
 #include <systemc.h>
 #include "../river_cfg.h"
-#include "../../../prj/impl/asic/target_cfg.h"
 #include "icache_lru.h"
 #include "dcache_lru.h"
 #include "pma.h"

diff --git a/sc/rtl/riverlib/l2cache/l2_top.h b/sc/rtl/riverlib/l2cache/l2_top.h
@@ -19,7 +19,6 @@
 #include "../../ambalib/types_amba.h"
 #include "../types_river.h"
 #include "../river_cfg.h"
-#include "../../../prj/impl/asic/target_cfg.h"
 #include "l2cache_lru.h"
 #include "l2_amba.h"
 #include "l2_dst.h"

diff --git a/sc/rtl/riverlib/river_amba.h b/sc/rtl/riverlib/river_amba.h
@@ -19,7 +19,6 @@
 #include "../ambalib/types_amba.h"
 #include "types_river.h"
 #include "river_cfg.h"
-#include "../../prj/impl/asic/target_cfg.h"
 #include "river_top.h"
 
 namespace debugger {

diff --git a/sc/rtl/riverlib/river_top.h b/sc/rtl/riverlib/river_top.h
@@ -17,7 +17,6 @@
 
 #include <systemc.h>
 #include "river_cfg.h"
-#include "../../prj/impl/asic/target_cfg.h"
 #include "core/proc.h"
 #include "cache/cache_top.h"
 

diff --git a/sc/rtl/riverlib/workgroup.h b/sc/rtl/riverlib/workgroup.h
@@ -20,7 +20,6 @@
 #include "../ambalib/types_pnp.h"
 #include "river_cfg.h"
 #include "types_river.h"
-#include "../../prj/impl/asic/target_cfg.h"
 #include "dmi/dmidebug.h"
 #include "dmi/ic_dport.h"
 #include "ic_axi4_to_l1.h"

diff --git a/sc/rtl/sdctrl/sdctrl_cache.cpp b/sc/rtl/sdctrl/sdctrl_cache.cpp
@@ -46,7 +46,6 @@ sdctrl_cache::sdctrl_cache(sc_module_name name,
     o_flush_end("o_flush_end") {
 
     async_reset_ = async_reset;
-    FLUSH_ALL_VALUE = ((1 << ibits) - 1);
     mem0 = 0;
 
     mem0 = new TagMem<abus,

diff --git a/sc/rtl/sdctrl/sdctrl_cache.h b/sc/rtl/sdctrl/sdctrl_cache.h
@@ -62,7 +62,6 @@ SC_MODULE(sdctrl_cache) {
 
  private:
     bool async_reset_;
-    uint32_t FLUSH_ALL_VALUE;
 
     static const int abus = CFG_SDCACHE_ADDR_BITS;
     static const int ibits = CFG_LOG2_SDCACHE_LINEBITS;
@@ -84,6 +83,7 @@ SC_MODULE(sdctrl_cache) {
     static const uint8_t State_ResetWrite = 11;
 
     static const uint64_t LINE_BYTES_MASK = ((1 << CFG_LOG2_SDCACHE_BYTES_PER_LINE) - 1);
+    static const uint32_t FLUSH_ALL_VALUE = ((1 << ibits) - 1);
 
     struct sdctrl_cache_registers {
         sc_signal<bool> req_write;