Skip to content

improve RISC-V multi core boot #330

improve RISC-V multi core boot

improve RISC-V multi core boot #330

Triggered via pull request August 13, 2023 17:17
Status Success
Total duration 13m 59s
Artifacts
This run and associated checks have been archived and are scheduled for deletion. Learn more about checks retention

sel4test-sim.yml

on: pull_request
Matrix: Simulation
Fit to window
Zoom out
Zoom in