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feat/x0: rename rd_internal
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Aurélien Nicolas committed Oct 31, 2024
1 parent 0f5ef92 commit e4e1aa5
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Showing 4 changed files with 8 additions and 7 deletions.
9 changes: 5 additions & 4 deletions ceno_emul/src/rv32im.rs
Original file line number Diff line number Diff line change
Expand Up @@ -226,8 +226,9 @@ impl DecodedInstruction {
self.opcode
}

/// Get the register destination, or RD_NULL if the instruction does not write to a register or writes to x0.
pub fn rd_or_null(&self) -> u32 {
/// The internal register destination. It is either the regular rd, or an internal RD_NULL if
/// the instruction does not write to a register or writes to x0.
pub fn rd_internal(&self) -> u32 {
match self.codes().format {
R | I | U | J if self.rd != 0 => self.rd,
_ => Self::RD_NULL,
Expand Down Expand Up @@ -690,7 +691,7 @@ impl Emulator {
if !new_pc.is_aligned() {
return ctx.trap(TrapCause::InstructionAddressMisaligned);
}
ctx.store_register(decoded.rd_or_null() as usize, out)?;
ctx.store_register(decoded.rd_internal() as usize, out)?;
ctx.set_pc(new_pc);
Ok(true)
}
Expand Down Expand Up @@ -777,7 +778,7 @@ impl Emulator {
}
_ => unreachable!(),
};
ctx.store_register(decoded.rd_or_null() as usize, out)?;
ctx.store_register(decoded.rd_internal() as usize, out)?;
ctx.set_pc(ctx.get_pc() + WORD_SIZE);
Ok(true)
}
Expand Down
2 changes: 1 addition & 1 deletion ceno_emul/src/tracer.rs
Original file line number Diff line number Diff line change
Expand Up @@ -215,7 +215,7 @@ impl StepRecord {
}),
rd: rd.map(|rd| WriteOp {
addr: CENO_PLATFORM
.register_vma(insn.rd_or_null() as RegIdx)
.register_vma(insn.rd_internal() as RegIdx)
.into(),
value: rd,
previous_cycle,
Expand Down
2 changes: 1 addition & 1 deletion ceno_zkvm/src/instructions/riscv/insn_base.rs
Original file line number Diff line number Diff line change
Expand Up @@ -223,7 +223,7 @@ impl<E: ExtensionField> WriteRD<E> {
lk_multiplicity: &mut LkMultiplicity,
step: &StepRecord,
) -> Result<(), ZKVMError> {
set_val!(instance, self.id, step.insn().rd_or_null() as u64);
set_val!(instance, self.id, step.insn().rd_internal() as u64);
set_val!(instance, self.prev_ts, step.rd().unwrap().previous_cycle);

// Register state
Expand Down
2 changes: 1 addition & 1 deletion ceno_zkvm/src/tables/program.rs
Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,7 @@ impl InsnRecord<u32> {
InsnRecord([
pc,
insn.opcode(),
insn.rd_or_null(),
insn.rd_internal(),
insn.funct3_or_zero(),
insn.rs1_or_zero(),
insn.rs2_or_zero(),
Expand Down

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