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Merge branch 'master' into mathias/use-sum
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matthiasgoergens authored Dec 12, 2024
2 parents 4c597d9 + 0cd9258 commit c7fe924
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Showing 26 changed files with 64 additions and 189 deletions.
11 changes: 2 additions & 9 deletions .github/workflows/integration.yml
Original file line number Diff line number Diff line change
Expand Up @@ -32,13 +32,6 @@ jobs:
timeout-minutes: 30
runs-on: [self-hosted, Linux, X64]

strategy:
matrix:
target: [x86_64-unknown-linux-gnu, riscv32im-unknown-none-elf]
# Exclude the riscv32im-unknown-none-elf target
exclude:
- target: riscv32im-unknown-none-elf

steps:
- uses: actions/checkout@v2
- name: Cargo cache
Expand All @@ -57,11 +50,11 @@ jobs:
env:
RAYON_NUM_THREADS: 2
RUSTFLAGS: "-C opt-level=3"
run: cargo run --package ceno_zkvm --example riscv_opcodes --target ${{ matrix.target }} -- --start 10 --end 11
run: cargo run --package ceno_zkvm --example riscv_opcodes -- --start 10 --end 11

- name: Run fibonacci
env:
RAYON_NUM_THREADS: 8
RUST_LOG: debug
RUSTFLAGS: "-C opt-level=3"
run: cargo run --package ceno_zkvm --bin e2e --target ${{ matrix.target }} -- --platform=sp1 ceno_zkvm/examples/fibonacci.elf
run: cargo run --package ceno_zkvm --bin e2e -- --platform=sp1 ceno_zkvm/examples/fibonacci.elf
8 changes: 0 additions & 8 deletions .github/workflows/lints.yml
Original file line number Diff line number Diff line change
Expand Up @@ -32,13 +32,6 @@ jobs:
timeout-minutes: 30
runs-on: [self-hosted, Linux, X64]

strategy:
matrix:
target: [x86_64-unknown-linux-gnu, riscv32im-unknown-none-elf]
# Exclude the riscv32im-unknown-none-elf target
exclude:
- target: riscv32im-unknown-none-elf

steps:
- uses: actions/checkout@v2
- uses: dtolnay/rust-toolchain@master
Expand Down Expand Up @@ -67,7 +60,6 @@ jobs:

- name: Run clippy
env:
TARGET: ${{ matrix.target }}
RUSTFLAGS: "-Dwarnings"
run: |
cargo check --workspace --all-targets --exclude ceno_rt
Expand Down
9 changes: 0 additions & 9 deletions .github/workflows/tests.yml
Original file line number Diff line number Diff line change
Expand Up @@ -31,13 +31,6 @@ jobs:
timeout-minutes: 30
runs-on: [self-hosted, Linux, X64]

strategy:
matrix:
target: [x86_64-unknown-linux-gnu, riscv32im-unknown-none-elf]
# Exclude the riscv32im-unknown-none-elf target
exclude:
- target: riscv32im-unknown-none-elf

steps:
- uses: actions/checkout@v2
- uses: dtolnay/rust-toolchain@master
Expand All @@ -61,6 +54,4 @@ jobs:
run: |
cargo make --version || cargo install cargo-make
- name: run test
env:
TARGET: ${{ matrix.target }}
run: cargo make tests
16 changes: 0 additions & 16 deletions Makefile.toml
Original file line number Diff line number Diff line change
@@ -1,20 +1,8 @@
[env]
CARGO_MAKE_EXTEND_WORKSPACE_MAKEFILE = true
CORE = { script = ["nproc"] }
CUR_TARGET = { script = ['''
if [ -z "${TARGET}" ]; then
TARGET=$(rustc -vV | grep "host" | awk '{print $2}')
echo "${TARGET}"
else
echo "${TARGET}"
fi
'''] }
RAYON_NUM_THREADS = "${CORE}"

[tasks.build]
# Override the default `--all-features`, that's broken, because some of our features are mutually exclusive.
args = ["build"]

[tasks.tests]
args = [
"test",
Expand All @@ -24,8 +12,6 @@ args = [
"--tests",
"--examples",
"--release",
"--target",
"${CUR_TARGET}",
"--workspace",
"--exclude",
"ceno_rt",
Expand All @@ -50,8 +36,6 @@ args = [
"--all-targets",
"--exclude",
"ceno_rt",
"--target",
"${CUR_TARGET}",
"--",
"-D",
"warnings",
Expand Down
5 changes: 1 addition & 4 deletions ceno_zkvm/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -52,12 +52,9 @@ pprof2.workspace = true
glob = "0.3"

[features]
default = ["riv32", "forbid_overflow"]
default = ["forbid_overflow"]
flamegraph = ["pprof2/flamegraph", "pprof2/criterion"]
forbid_overflow = []
non_pow2_rayon_thread = []
riv32 = []
riv64 = []

[[bench]]
harness = false
Expand Down
10 changes: 5 additions & 5 deletions ceno_zkvm/src/chip_handler.rs
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ use ff_ext::ExtensionField;
use crate::{
error::ZKVMError,
expression::{Expression, ToExpr},
gadgets::AssertLTConfig,
gadgets::AssertLtConfig,
instructions::riscv::constants::UINT_LIMBS,
};

Expand Down Expand Up @@ -34,7 +34,7 @@ pub trait RegisterChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce(
prev_ts: Expression<E>,
ts: Expression<E>,
value: RegisterExpr<E>,
) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;

#[allow(clippy::too_many_arguments)]
fn register_write(
Expand All @@ -45,7 +45,7 @@ pub trait RegisterChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce(
ts: Expression<E>,
prev_values: RegisterExpr<E>,
value: RegisterExpr<E>,
) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
}

/// The common representation of a memory address.
Expand All @@ -62,7 +62,7 @@ pub trait MemoryChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce()
prev_ts: Expression<E>,
ts: Expression<E>,
value: MemoryExpr<E>,
) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;

#[allow(clippy::too_many_arguments)]
fn memory_write(
Expand All @@ -73,5 +73,5 @@ pub trait MemoryChipOperations<E: ExtensionField, NR: Into<String>, N: FnOnce()
ts: Expression<E>,
prev_values: MemoryExpr<E>,
value: MemoryExpr<E>,
) -> Result<(Expression<E>, AssertLTConfig), ZKVMError>;
) -> Result<(Expression<E>, AssertLtConfig), ZKVMError>;
}
10 changes: 5 additions & 5 deletions ceno_zkvm/src/chip_handler/memory.rs
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ use crate::{
circuit_builder::CircuitBuilder,
error::ZKVMError,
expression::Expression,
gadgets::AssertLTConfig,
gadgets::AssertLtConfig,
instructions::riscv::constants::UINT_LIMBS,
structs::RAMType,
};
Expand All @@ -19,7 +19,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
prev_ts: Expression<E>,
ts: Expression<E>,
value: MemoryExpr<E>,
) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
self.namespace(name_fn, |cb| {
// READ (a, v, t)
let read_record = [
Expand All @@ -39,7 +39,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
cb.write_record(|| "write_record", RAMType::Memory, write_record)?;

// assert prev_ts < current_ts
let lt_cfg = AssertLTConfig::construct_circuit(
let lt_cfg = AssertLtConfig::construct_circuit(
cb,
|| "prev_ts < ts",
prev_ts,
Expand All @@ -61,7 +61,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
ts: Expression<E>,
prev_values: MemoryExpr<E>,
value: MemoryExpr<E>,
) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
self.namespace(name_fn, |cb| {
// READ (a, v, t)
let read_record = [
Expand All @@ -80,7 +80,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> MemoryChipOperation
cb.read_record(|| "read_record", RAMType::Memory, read_record)?;
cb.write_record(|| "write_record", RAMType::Memory, write_record)?;

let lt_cfg = AssertLTConfig::construct_circuit(
let lt_cfg = AssertLtConfig::construct_circuit(
cb,
|| "prev_ts < ts",
prev_ts,
Expand Down
10 changes: 5 additions & 5 deletions ceno_zkvm/src/chip_handler/register.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ use crate::{
circuit_builder::CircuitBuilder,
error::ZKVMError,
expression::{Expression, ToExpr},
gadgets::AssertLTConfig,
gadgets::AssertLtConfig,
instructions::riscv::constants::UINT_LIMBS,
structs::RAMType,
};
Expand All @@ -21,7 +21,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
prev_ts: Expression<E>,
ts: Expression<E>,
value: RegisterExpr<E>,
) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
self.namespace(name_fn, |cb| {
// READ (a, v, t)
let read_record = [
Expand All @@ -43,7 +43,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
cb.write_record(|| "write_record", RAMType::Register, write_record)?;

// assert prev_ts < current_ts
let lt_cfg = AssertLTConfig::construct_circuit(
let lt_cfg = AssertLtConfig::construct_circuit(
cb,
|| "prev_ts < ts",
prev_ts,
Expand All @@ -65,7 +65,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
ts: Expression<E>,
prev_values: RegisterExpr<E>,
value: RegisterExpr<E>,
) -> Result<(Expression<E>, AssertLTConfig), ZKVMError> {
) -> Result<(Expression<E>, AssertLtConfig), ZKVMError> {
assert!(register_id.expr().degree() <= 1);
self.namespace(name_fn, |cb| {
// READ (a, v, t)
Expand All @@ -87,7 +87,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
cb.read_record(|| "read_record", RAMType::Register, read_record)?;
cb.write_record(|| "write_record", RAMType::Register, write_record)?;

let lt_cfg = AssertLTConfig::construct_circuit(
let lt_cfg = AssertLtConfig::construct_circuit(
cb,
|| "prev_ts < ts",
prev_ts,
Expand Down
16 changes: 4 additions & 12 deletions ceno_zkvm/src/expression.rs
Original file line number Diff line number Diff line change
Expand Up @@ -591,17 +591,17 @@ macro_rules! mixed_binop_instances {
mixed_binop_instances!(
Add,
add,
(u8, u16, u32, u64, usize, i8, i16, i32, i64, i128, isize)
(u8, u16, u32, u64, usize, i8, i16, i32, i64, isize)
);
mixed_binop_instances!(
Sub,
sub,
(u8, u16, u32, u64, usize, i8, i16, i32, i64, i128, isize)
(u8, u16, u32, u64, usize, i8, i16, i32, i64, isize)
);
mixed_binop_instances!(
Mul,
mul,
(u8, u16, u32, u64, usize, i8, i16, i32, i64, i128, isize)
(u8, u16, u32, u64, usize, i8, i16, i32, i64, isize)
);

impl<E: ExtensionField> Mul for Expression<E> {
Expand Down Expand Up @@ -840,14 +840,6 @@ macro_rules! impl_from_unsigned {
}
impl_from_unsigned!(u8, u16, u32, u64, usize, RAMType, InsnKind);

// Implement From trait for u128 separately since it requires explicit reduction
impl<F: SmallField, E: ExtensionField<BaseField = F>> From<u128> for Expression<E> {
fn from(value: u128) -> Self {
let reduced = value.rem_euclid(F::MODULUS_U64 as u128) as u64;
Expression::Constant(F::from(reduced))
}
}

// Implement From trait for signed types
macro_rules! impl_from_signed {
($($t:ty),*) => {
Expand All @@ -861,7 +853,7 @@ macro_rules! impl_from_signed {
)*
};
}
impl_from_signed!(i8, i16, i32, i64, i128, isize);
impl_from_signed!(i8, i16, i32, i64, isize);

impl<E: ExtensionField> Display for Expression<E> {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
Expand Down
6 changes: 3 additions & 3 deletions ceno_zkvm/src/gadgets/div.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,13 +10,13 @@ use crate::{
witness::LkMultiplicity,
};

use super::AssertLTConfig;
use super::AssertLtConfig;

/// divide gadget
#[derive(Debug, Clone)]
pub struct DivConfig<E: ExtensionField> {
pub dividend: UInt<E>,
pub r_lt: AssertLTConfig,
pub r_lt: AssertLtConfig,
pub intermediate_mul: UInt<E>,
}

Expand All @@ -35,7 +35,7 @@ impl<E: ExtensionField> DivConfig<E> {
let (dividend, intermediate_mul) =
divisor.mul_add(|| "divisor * outcome + r", cb, quotient, remainder, true)?;

let r_lt = AssertLTConfig::construct_circuit(
let r_lt = AssertLtConfig::construct_circuit(
cb,
|| "remainder < divisor",
remainder.value(),
Expand Down
4 changes: 2 additions & 2 deletions ceno_zkvm/src/gadgets/is_lt.rs
Original file line number Diff line number Diff line change
Expand Up @@ -19,9 +19,9 @@ use crate::{
use super::SignedExtendConfig;

#[derive(Debug, Clone)]
pub struct AssertLTConfig(InnerLtConfig);
pub struct AssertLtConfig(InnerLtConfig);

impl AssertLTConfig {
impl AssertLtConfig {
pub fn construct_circuit<
E: ExtensionField,
NR: Into<String> + Display + Clone,
Expand Down
2 changes: 1 addition & 1 deletion ceno_zkvm/src/gadgets/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ mod signed_ext;

pub use div::DivConfig;
pub use is_lt::{
AssertLTConfig, AssertSignedLtConfig, InnerLtConfig, IsLtConfig, SignedLtConfig, cal_lt_diff,
AssertLtConfig, AssertSignedLtConfig, InnerLtConfig, IsLtConfig, SignedLtConfig, cal_lt_diff,
};
pub use is_zero::{IsEqualConfig, IsZeroConfig};
pub use signed_ext::SignedExtendConfig;
4 changes: 1 addition & 3 deletions ceno_zkvm/src/instructions/riscv/constants.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,8 @@ pub const PUBLIC_IO_IDX: usize = 6;
pub const LIMB_BITS: usize = 16;
pub const LIMB_MASK: u32 = 0xFFFF;

#[cfg(feature = "riv32")]
pub const BIT_WIDTH: usize = 32usize;
#[cfg(feature = "riv64")]
pub const BIT_WIDTH: usize = 64usize;

pub type UInt<E> = UIntLimbs<BIT_WIDTH, LIMB_BITS, E>;
pub type UIntMul<E> = UIntLimbs<{ 2 * BIT_WIDTH }, LIMB_BITS, E>;
/// use UInt<x> for x bits limb size
Expand Down
4 changes: 2 additions & 2 deletions ceno_zkvm/src/instructions/riscv/ecall/halt.rs
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ use crate::{
circuit_builder::CircuitBuilder,
error::ZKVMError,
expression::{ToExpr, WitIn},
gadgets::AssertLTConfig,
gadgets::AssertLtConfig,
instructions::{
Instruction,
riscv::{
Expand All @@ -21,7 +21,7 @@ use std::{marker::PhantomData, mem::MaybeUninit};
pub struct HaltConfig {
ecall_cfg: EcallInstructionConfig,
prev_x10_ts: WitIn,
lt_x10_cfg: AssertLTConfig,
lt_x10_cfg: AssertLtConfig,
}

pub struct HaltInstruction<E>(PhantomData<E>);
Expand Down
4 changes: 2 additions & 2 deletions ceno_zkvm/src/instructions/riscv/ecall_insn.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ use crate::{
circuit_builder::CircuitBuilder,
error::ZKVMError,
expression::{Expression, ToExpr, WitIn},
gadgets::AssertLTConfig,
gadgets::AssertLtConfig,
set_val,
tables::InsnRecord,
witness::LkMultiplicity,
Expand All @@ -18,7 +18,7 @@ pub struct EcallInstructionConfig {
pub pc: WitIn,
pub ts: WitIn,
prev_x5_ts: WitIn,
lt_x5_cfg: AssertLTConfig,
lt_x5_cfg: AssertLtConfig,
}

impl EcallInstructionConfig {
Expand Down
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