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Merge remote-tracking branch 'origin/master' into matthias/plane
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matthiasgoergens committed Oct 29, 2024
2 parents 9f813c9 + 70fbefc commit 8356a9d
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Showing 28 changed files with 74 additions and 1,158 deletions.
1 change: 0 additions & 1 deletion ceno_emul/src/rv32im.rs
Original file line number Diff line number Diff line change
Expand Up @@ -88,7 +88,6 @@ pub struct Emulator {
}

#[derive(Debug)]
#[allow(dead_code)]
pub enum TrapCause {
InstructionAddressMisaligned,
InstructionAccessFault,
Expand Down
93 changes: 7 additions & 86 deletions ceno_zkvm/src/instructions/riscv/arith.rs
Original file line number Diff line number Diff line change
Expand Up @@ -171,8 +171,6 @@ impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for ArithInstruction<E
mod test {
use ceno_emul::{Change, StepRecord, encode_rv32};
use goldilocks::GoldilocksExt2;
use itertools::Itertools;
use multilinear_extensions::mle::IntoMLEs;

use super::*;
use crate::{
Expand Down Expand Up @@ -222,18 +220,7 @@ mod test {
.require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}

#[test]
Expand Down Expand Up @@ -277,18 +264,7 @@ mod test {
.require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}

#[test]
Expand Down Expand Up @@ -332,18 +308,7 @@ mod test {
.require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}

#[test]
Expand Down Expand Up @@ -387,18 +352,7 @@ mod test {
.require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
None,
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, None);
}

#[test]
Expand Down Expand Up @@ -434,18 +388,7 @@ mod test {
.require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}

#[test]
Expand Down Expand Up @@ -480,18 +423,7 @@ mod test {
.require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}

#[test]
Expand Down Expand Up @@ -534,17 +466,6 @@ mod test {
.require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}
}
28 changes: 2 additions & 26 deletions ceno_zkvm/src/instructions/riscv/arith_imm.rs
Original file line number Diff line number Diff line change
Expand Up @@ -83,8 +83,6 @@ impl<E: ExtensionField> Instruction<E> for AddiInstruction<E> {
mod test {
use ceno_emul::{Change, InsnKind, PC_STEP_SIZE, StepRecord, encode_rv32};
use goldilocks::GoldilocksExt2;
use itertools::Itertools;
use multilinear_extensions::mle::IntoMLEs;

use crate::{
circuit_builder::{CircuitBuilder, ConstraintSystem},
Expand Down Expand Up @@ -124,18 +122,7 @@ mod test {
)
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}

#[test]
Expand Down Expand Up @@ -168,17 +155,6 @@ mod test {
)
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}
}
2 changes: 0 additions & 2 deletions ceno_zkvm/src/instructions/riscv/b_insn.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,3 @@
#![allow(dead_code)] // TODO: remove after BLT, BEQ, …

use ceno_emul::{InsnKind, StepRecord};
use ff_ext::ExtensionField;

Expand Down
80 changes: 6 additions & 74 deletions ceno_zkvm/src/instructions/riscv/branch/test.rs
Original file line number Diff line number Diff line change
@@ -1,7 +1,5 @@
use ceno_emul::{ByteAddr, Change, PC_STEP_SIZE, StepRecord, Word, encode_rv32};
use goldilocks::GoldilocksExt2;
use itertools::Itertools;
use multilinear_extensions::mle::IntoMLEs;

use super::*;
use crate::{
Expand Down Expand Up @@ -49,18 +47,7 @@ fn impl_opcode_beq(equal: bool) {
])
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}

#[test]
Expand Down Expand Up @@ -98,18 +85,7 @@ fn impl_opcode_bne(equal: bool) {
])
.unwrap();

MockProver::assert_satisfied(
&cb,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm));
}

#[test]
Expand Down Expand Up @@ -150,18 +126,7 @@ fn impl_bltu_circuit(taken: bool, a: u32, b: u32) -> Result<(), ZKVMError> {
])
.unwrap();

MockProver::assert_satisfied(
&circuit_builder,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&circuit_builder, raw_witin, &[insn_code], None, Some(lkm));
Ok(())
}

Expand Down Expand Up @@ -202,18 +167,7 @@ fn impl_bgeu_circuit(taken: bool, a: u32, b: u32) -> Result<(), ZKVMError> {
])
.unwrap();

MockProver::assert_satisfied(
&circuit_builder,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&circuit_builder, raw_witin, &[insn_code], None, Some(lkm));
Ok(())
}

Expand Down Expand Up @@ -255,18 +209,7 @@ fn impl_blt_circuit(taken: bool, a: i32, b: i32) -> Result<(), ZKVMError> {
])
.unwrap();

MockProver::assert_satisfied(
&circuit_builder,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&circuit_builder, raw_witin, &[insn_code], None, Some(lkm));
Ok(())
}

Expand Down Expand Up @@ -308,17 +251,6 @@ fn impl_bge_circuit(taken: bool, a: i32, b: i32) -> Result<(), ZKVMError> {
])
.unwrap();

MockProver::assert_satisfied(
&circuit_builder,
&raw_witin
.de_interleaving()
.into_mles()
.into_iter()
.map(|v| v.into())
.collect_vec(),
&[insn_code],
None,
Some(lkm),
);
MockProver::assert_satisfied_raw(&circuit_builder, raw_witin, &[insn_code], None, Some(lkm));
Ok(())
}
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