feat/x0: branch instructions do not write rd

ceno_emul/src/rv32im.rs

@@ -576,7 +576,9 @@ impl Emulator {
         let pc = ctx.get_pc();
         let mut new_pc = pc + WORD_SIZE;
         let imm_i = decoded.imm_i();
+        let mut skip_rd = false;
         let mut br_cond = |cond| -> u32 {
+            skip_rd = true;
             if cond {
                 new_pc = pc.wrapping_add(decoded.imm_b());
             }
@@ -700,7 +702,9 @@ impl Emulator {
         if !new_pc.is_aligned() {
             return ctx.trap(TrapCause::InstructionAddressMisaligned);
         }
-        ctx.store_register(decoded.rd_or_null() as usize, out)?;
+        if !skip_rd {
+            ctx.store_register(decoded.rd_or_null() as usize, out)?;
+        }
         ctx.set_pc(new_pc);
         Ok(true)
     }

ceno_zkvm/examples/riscv_opcodes.rs

@@ -27,7 +27,7 @@ use tracing_flame::FlameLayer;
 use tracing_subscriber::{EnvFilter, Registry, fmt, layer::SubscriberExt};
 use transcript::Transcript;
 
-const PROGRAM_SIZE: usize = 512;
+const PROGRAM_SIZE: usize = 16;
 // For now, we assume registers
 //  - x0 is not touched,
 //  - x1 is initialized to 1,
@@ -192,6 +192,7 @@ fn main() {
                         cycle: *final_access.get(&vma).unwrap_or(&0),
                     }
                 } else {
+                    // The table is padded beyond the number of registers.
                     MemFinalRecord { value: 0, cycle: 0 }
                 }
             })

ceno_zkvm/src/tables/program.rs

@@ -161,6 +161,7 @@ impl<E: ExtensionField, const PROGRAM_SIZE: usize> TableCircuit<E>
         let pc_base = program.base_address;
 
         let mut fixed = RowMajorMatrix::<E::BaseField>::new(num_instructions, num_fixed);
+        Self::padding_zero(&mut fixed, num_fixed).expect("padding error");
 
         fixed
             .par_iter_mut()