Skip to content

Spartan-6 Verilog binary counter using 4 bits by slowing down the clock. Buzzer uses the tone from the counter, and sound from input.

Notifications You must be signed in to change notification settings

ryancor/FPGA-ClkDivider

Repository files navigation

FPGA-ClkDivider

I/O Planning

About

Spartan-6 Verilog binary counter using 4 bits by slowing down the clock. Buzzer uses the tone from the counter, and sound from input.

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published