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feat(embedded-hal-bus): Spi - Add support for cs to clock delay #605
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Thanks for the PR! This is a welcome addition, just a few notes:
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Thank you for the feedback! Note: If you ever encountered something similar and could give a quick tipwith the clock pin first bit floating for a while before starting normally under embassy_stm32: Maybe related to embassy-rs/embassy#1094 but I actually have no idea (timer prescaler config issue?), maybe you saw this in the past and could have quick tip? I will continue by testing on ESP32C3 awaiting I fix my issue on the STM32. |
it might be a bug yes. please file an issue or join #embassy, we can discuss there. |
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Fix wrong variable name in spi shared delay driver
…vice-impls-for-CS-to-clock-delays
Issue created and solve at embassy-rs/embassy#3039 |
What
Add support for cs to clock delay in
embedded-hal-bus
spi's device implementation.Resolves #539
Why
This feature is defined at https://docs.rs/embedded-hal/latest/embedded_hal/spi/index.html#cs-to-clock-delays and issued at #539
Some chips that communicates through SPI necessitate this feature in order to correctly communicate.
How
Added a field in the device structs in order to store the
cs_to_clock_delay
, with its adequate constructor parameter.The delay is applied in the shared transaction implementation, just after the CS is toggled.
Notes
core::time::Duration
in the code, I would like to know if its a bad practice in embedded system implementation or not and why