Add optional backend for critical-section
#191
Merged
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This is similar to the single-threaded bare metal implementations in
cortex-m
andriscv
.In theory there could be a race condition in
acquire
if an interrupt occurs between theread
andwrite
, and the interrupt disablesIME
. But it's probably not sensible to have an interrupt disable interrupts, so I don't think it's necessarily to complicate things with inline assembly usingswp
.