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risingwavelabs · Jul 24, 2024 · 57706c6 · 57706c6
1 parent 4801f13
commit 57706c6
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Showing 2 changed files with 1 addition and 3 deletions.
diff --git a/src/frontend/src/optimizer/plan_node/logical_agg.rs b/src/frontend/src/optimizer/plan_node/logical_agg.rs
@@ -645,6 +645,7 @@ impl LogicalAggBuilder {
             }
             AggKind::ApproxPercentile => {
                 if agg_call.order_by.sort_exprs[0].order_type == OrderType::descending() {
+                    // Rewrite DESC into 1.0-percentile for approx_percentile.
                     let prev_percentile = agg_call.direct_args[0].clone();
                     let new_percentile = 1.0
                         - prev_percentile

diff --git a/src/frontend/src/optimizer/plan_node/stream_keyed_merge.rs b/src/frontend/src/optimizer/plan_node/stream_keyed_merge.rs
@@ -74,7 +74,6 @@ impl StreamKeyedMerge {
         let schema = Schema::new(schema_fields);
         let watermark_columns = FixedBitSet::with_capacity(schema.fields.len());
 
-        // FIXME: schema is wrong.
         let base = PlanBase::new_stream(
             lhs_input.ctx(),
             schema,
@@ -99,8 +98,6 @@ impl StreamKeyedMerge {
 impl Distill for StreamKeyedMerge {
     fn distill<'a>(&self) -> XmlNode<'a> {
         let mut out = Vec::with_capacity(1);
-        // out.push(("lhs_col_mapping", Pretty::debug(&self.lhs_mapping)));
-        // out.push(("rhs_col_mapping", Pretty::debug(&self.rhs_mapping)));
 
         if self.base.ctx().is_explain_verbose() {
             let f = |t| Pretty::debug(&t);