Minor fixes #54
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Minor fixes #54
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jrtc27
reviewed
Jan 26, 2024
jrtc27
reviewed
Jan 26, 2024
jrtc27
reviewed
Jan 26, 2024
src/riscv-integration.adoc
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| @@ -1058,7 +1059,7 @@ NOTE: `auth_cap` is <<ddc>> for Legacy mode and `cs1` for Capability Mode | |||
| 6+| *Store/atomic/cache-block-operation additional exception checks* | |||
| | all stores, all atomics, all cbos | {cheri_excep_mcause} | {cheri_excep_type_data} | {cheri_excep_cause_tag} |`auth_cap` tag | not(`auth_cap.tag`) | |||
| | all stores, all atomics, all cbos | {cheri_excep_mcause} | {cheri_excep_type_data} | {cheri_excep_cause_seal} |`auth_cap` seal | isCapSealed(`auth_cap`) | |||
| | all atomics, all cbos | {cheri_excep_mcause} | {cheri_excep_type_data} | {cheri_excep_cause_perm} |`auth_cap` permission | AMO only: not(`auth_cap`.<<r_perm>>) | |||
| | all atomics | {cheri_excep_mcause} | {cheri_excep_type_data} | {cheri_excep_cause_perm} |`auth_cap` permission | not(`auth_cap`.<<r_perm>>) | |||
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CBO.ZERO is equivalent to a series of writes, so it shouldn't check R. FLUSH/INVAL are less critical but are more writey than ready.
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There were previous discussions about what permissions to check for each CBO. The checks are summarised here for all CBO and prefetch instructions. These checks are currently specified in the instruction listings towards the end of the spec, so ideally we can stick with these unless there is a clear problem:
- cbo.zero is a whole cache line store, so it behaves and is checked exactly like any other RISC-V store
- Bounds, tag, store permission, etc are checked
- There are two variants of the instruction depending on the PCC mode flag
- prefetch.i, prefetch.r and prefetch.w
- Tag and sealing check as usual
- prefetch.i check execute permission
- prefetch.w check store permission
- prefetch.r check load permission
- Check that the authorising capability's bounds cover at least 1 byte in the cache line prefetched
- Do not start the prefetch if any of the checks above fails.
- cbo.clean and cbo.flush
- Tag and sealing check as usual
- Check that there are store or load permissions
- Check that the authorising capability's bounds cover at least 1 byte in the cache line flushed/cleaned
- cbo.inval
- Tag and sealing check as usual
- Check that there are store, load and ASR permissions
- Check that the authorising capability's bounds cover the entire cache line invalidated
- The same checks must be retained if cbo.inval is configured to behave as cbo.flush
andresag01
reviewed
Jan 26, 2024
src/riscv-integration.adoc
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| | indirect jumps | {cheri_excep_mcause} | {cheri_excep_type_jump} | {cheri_excep_cause_tag} |`cs1` tag | not(`cs1.tag`) | ||
| | indirect jumps | {cheri_excep_mcause} | {cheri_excep_type_jump} | {cheri_excep_cause_seal} |`cs1` seal | isCapSealed(`cs1`) and imm12 != 0 | ||
| | indirect jumps | {cheri_excep_mcause} | {cheri_excep_type_jump} | {cheri_excep_cause_perm} |`cs1` permission| not(`cs1`.<<x_perm>>) | ||
| | indirect jumps | {cheri_excep_mcause} | {cheri_excep_type_jump} | {cheri_excep_cause_length} |`cs1` length | any byte of 16-bit instruction at target out of `cs1` bounds |
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The 16-bit must also be "minimal length"
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andresag01
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Feb 2, 2024
src/riscv-integration.adoc
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| sign-extended 12-bit immediate if the immediate is not zero, then setting the | ||
| least significant bit of the result to zero, then unsealing. The capability | ||
| with the address of the instruction following the jump (<<pcc>> + 4) is written | ||
| to a *c* register. |
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Could you change this to say that the return capability is sealed?
|
This change also fixes #84 |
The exception table for CMOs comes from CTSRD-CHERI/cheri-specification#65.
andresag01
approved these changes
Feb 2, 2024
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These are the items from my list that should mostly speak for themselves.