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Added missing description of changes to the hedeleg register #466

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Dec 12, 2024
Merged

Added missing description of changes to the hedeleg register #466

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56dce19
Added missing description of changes to the hedeleg register
francislaus Dec 9, 2024
45f726a
Changed description of hedeleg
francislaus Dec 12, 2024
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8 changes: 8 additions & 0 deletions src/hypervisor-integration.adoc
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Expand Up @@ -50,6 +50,14 @@ VU-mode as described in xref:section_cheri_disable[xrefstyle=short].

The reset value is 0.

[#hedeleg,reftext="hedeleg"]
=== Hypervisor Exception Delegation Register (hedeleg)

The <<hedeleg>> register operates as described in the RISC-V Privileged
Specification. At position 28, a new bit is added to <<hedeleg>>
when the implementation supports {cheri_base_ext_name}. This allows CHERI
exceptions to be delegated to VS mode.

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[#htval,reftext="htval"]
=== Hypervisor Trap Value Register (htval)

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