we need to specify their priorities

The global rule is that CHERI checks come first - and anything existing in RISC-V comes after.
Is there any reason why this wouldn't work here?

(the only counter-example is a PC breakpoint - which is higher than CHERI checks on the PC - otherwise it's impossible to debug CHERI code)

Also there's a question of what happens if hardware A/D bit updates are supported but hardware CRG/CW bit updates are not, or vice versa. It would simplify the Sail implementation (and spec!) if they always had to be the same - either all hardware updates or none at all. Would that be acceptable?

I've already tied them together in section 5.4 (@buxtonpaul asked about this before)

The global rule is that CHERI checks come first - and anything existing in RISC-V comes after.
Is there any reason why this wouldn't work here?

Ah ok, no I think that should be fine. Is that general rule written down anywhere?

I've already tied them together in section 5.4 (@buxtonpaul asked about this before)

Ah ok I missed that, thanks!

Ah ok, no I think that should be fine. Is that general rule written down anywhere?

I think the correct solution here is to add the PTE page faults into the exception check information on the instruction pages, and add the statement that the PTE page faults come first.

PR to follow