fix formatting

riscv · Nov 6, 2024 · fb976eb · fb976eb
1 parent b7c9d7e
commit fb976eb
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/src/cheri-pte-ext.adoc b/src/cheri-pte-ext.adoc
@@ -157,11 +157,11 @@ bit value of the capability read. This will introduce additional traps during re
 [#xstatus_pte]
 === Extending the Machine (mstatus), Supervisor (sstatus) and Virtual Supervisor (vsstatus) Status Registers
 
-The <<mstatusreg_pte,mstatus>>, <<sstatusreg_pte,status>> and <<vsstatusreg_pte,vsstatus>> CSRs are extended to include the new Capability Read Generation (CRG) bit as shown.
+The <<mstatusreg_pte,mstatus>>, <<sstatusreg_pte,sstatus>> and <<vsstatusreg_pte,vsstatus>> CSRs are extended to include the new Capability Read Generation (CRG) bit as shown.
 
-mstatus.CRG is made visible in sstatus.CRG.
+<<mstatusreg_pte,mstatus>>.CRG is made visible in <<sstatusreg_pte,sstatus>>.CRG.
 
-When V=1 vsstatus.CRG is in effect.
+When V=1 <<vsstatusreg_pte,vsstatus>>.CRG is in effect.
 
 [#mstatusreg_pte]
 .Machine-mode status (*mstatus*) register when MXLEN=64