Fix trailing whitespace

This was done automatically with `pre-commit run --all-files`.

CONTRIBUTING.md

@@ -55,4 +55,4 @@ You can manually add the DCO text to your commit body or include either -s or --
 
 Note:
 
-Ensure that the name and email address associated with your GitHub account match the name and email address in the Signed-off-by line of your commit message.
+Ensure that the name and email address associated with your GitHub account match the name and email address in the Signed-off-by line of your commit message.

LICENSE

@@ -49,7 +49,7 @@ exhaustive, and do not form part of our licenses.
      such as asking that all changes be marked or described.
      Although not required by our licenses, you are encouraged to
      respect those requests where reasonable. More_considerations
-     for the public: 
+     for the public:
 	wiki.creativecommons.org/Considerations_for_licensees
 
 =======================================================================
@@ -393,4 +393,3 @@ the avoidance of doubt, this paragraph does not form part of the
 public licenses.
 
 Creative Commons may be contacted at creativecommons.org.
-

src/cheri-pte-ext.adoc

@@ -97,4 +97,3 @@ bit is available for S-mode address translation. When CDE=0, the implementation
 behaves as though the CD bit were not implemented. If CD is not implemented,
 CDE is read-only zero. If CD is implemented although not configurable, CDE is
 read-only one.
-

src/csv/CHERI_CSR.csv

@@ -30,4 +30,4 @@ direct write if address didn't change","✔","","","✔","✔","Zcmt","Jump Vect
 "stdc","0x163","","","S","SRW, <<asr_perm>>","<<null-cap>>","","","","","","✔","","S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
 "ddc","0x416","","","U","URW","<<infinite-cap>>","","","","","","✔","","none","User Default Data Capability","","","","","","","","","","","","","","","","","","","","",""
 "pcc","0xcb0","","","U","URO","<<infinite-cap>>
-(address = boot address)","","","✔","","","✔","✔","none","User Program Counter Capability (to allow reading in legacy mode)","","","","","","","","","","","","","","","","","","","","",""
+(address = boot address)","","","✔","","","✔","✔","none","User Program Counter Capability (to allow reading in legacy mode)","","","","","","","","","","","","","","","","","","","","",""

src/csv/CHERI_ISA.csv

@@ -173,4 +173,4 @@
 "SH4ADD","","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","",""
 "SH4ADD.UW","","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","",""
 "CSH4ADD","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD","SH4ADD","shift and add, representability check on the result","","","","","","","",""
-"CSH4ADD.UW","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD.UW","SH4ADD.UW","shift and add, representability check on the result","","","","","","","",""
+"CSH4ADD.UW","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD.UW","SH4ADD.UW","shift and add, representability check on the result","","","","","","","",""

src/debug-integration.adoc

@@ -103,4 +103,3 @@ The <<dscratch1c>> register is a CLEN-bit plus tag bit extension to
 
 .Debug scratch 1 capability register
 include::img/dscratch1creg.edn[]
-

src/img/mtvalreg.edn

@@ -18,4 +18,3 @@
 (draw-box "12"       {:span 12 :borders {}})
 (draw-box "4"        {:span 4 :borders {}})
 ----
-

src/img/stvalreg.edn

@@ -18,4 +18,3 @@
 (draw-box "12"       {:span 12 :borders {}})
 (draw-box "4"        {:span 4 :borders {}})
 ----
-

src/insns/atomic_exceptions.adoc

@@ -30,4 +30,4 @@ reported in the CAUSE field of <<mtval>> or <<stval>>:
 | Length violation      | At least one byte accessed is outside the authority capability bounds
 |==============================================================================
 
-:!cap_atomic:
+:!cap_atomic:

src/insns/candperm_32bit.adoc

@@ -46,4 +46,3 @@ Operation::
 --
 TODO: Sail does not have the new encoding of the permissions field.
 --
-

src/insns/cbo.clean.adoc

@@ -53,4 +53,3 @@ Operation::
 --
 TBD
 --
-

src/insns/cbuildcap_32bit.adoc

@@ -45,4 +45,3 @@ Operation::
 --
 TODO: Original Sail looks at otype field, etc that don't exist
 --
-

src/insns/cgethigh_32bit.adoc

@@ -25,4 +25,3 @@ Operation:: TODO #this is correct but capToMemBits is redundant, as it's now XOR
 --
 TODO
 --
-

src/insns/cgetperm_32bit.adoc

@@ -29,4 +29,3 @@ Operation::
 --
 TODO: The encoding of permissions changed.
 --
-

src/insns/cgettag_32bit.adoc

@@ -23,4 +23,3 @@ Operation::
 --
 TODO
 --
-

src/insns/cincoffset_32bit.adoc

@@ -52,4 +52,3 @@ Operation (CINCOFFSETIMM)::
 --
 TODO
 --
-

src/insns/cj_j_16bit.adoc

@@ -45,4 +45,3 @@ Prerequisites for C.J::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CJAL>>, <<JAL>>
-

src/insns/cjal_jal_16bit.adoc

@@ -42,4 +42,3 @@ Prerequisites for C.JAL::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CJAL>>, <<JAL>>
-

src/insns/cjal_jal_common.adoc

@@ -5,4 +5,3 @@ Link the next linear <<pcc>> to `cd` and seal. Jump to <<pcc>>.address+offset.
 Legacy Mode Description::
 Set the next PC and link to `rd` according to the standard <<JAL>> definition.
  Check a minimum length instruction is in <<pcc>> bounds at the target PC, take a CHERI Length Violation exception on error.
-

src/insns/cjalr_jalr_16bit.adoc

@@ -42,4 +42,3 @@ Prerequisites C.JALR::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CJALR>>, <<JALR>>
-

src/insns/cjalr_jalr_32bit.adoc

@@ -72,4 +72,3 @@ JALR Operation::
 --
 TBD
 --
-

src/insns/cjr_jr_16bit.adoc

@@ -48,4 +48,3 @@ Prerequisites for C.JALR::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CJALR>>, <<JALR>>
-

src/insns/cmove_32bit.adoc

@@ -28,4 +28,3 @@ Operation::
 --
 TODO
 --
-

src/insns/condbr_16bit.adoc

@@ -23,4 +23,3 @@ C or Zca
 
 Operation (after expansion to 32-bit encodings)::
  See <<insns-conbr-32bit>>
-

src/insns/cram_32bit.adoc

@@ -25,4 +25,3 @@ Operation::
 --
 TODO
 --
-

src/insns/cseal_32bit.adoc

@@ -26,4 +26,3 @@ Operation::
 --
 TODO: The SAIL definition for CSEAL writes the OTYPE which does not exist anymore.
 --
-

src/insns/csetaddr_32bit.adoc

@@ -28,4 +28,3 @@ Operation::
 --
 TODO
 --
-

src/insns/csetequalexact_32bit.adoc

@@ -26,4 +26,3 @@ Operation::
 --
 TODO
 --
-

src/insns/csethigh_32bit.adoc

@@ -26,4 +26,3 @@ Operation:: TODO #this is correct but capToMemBits is redundant, as it's now XOR
 --
 TODO
 --
-

src/insns/csetmode_32bit.adoc

@@ -30,4 +30,3 @@ Operation ::
 --
 TODO
 --
-

src/insns/ctestsubset_32bit.adoc

@@ -29,4 +29,3 @@ Operation::
 --
 TODO
 --
-

src/insns/load_16bit.adoc

@@ -70,5 +70,3 @@ Prerequisites C.LW::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CLD>>, <<CLW>>, <<LD>>, <<LW>>
-
-

src/insns/load_16bit_Zcb.adoc

@@ -63,5 +63,3 @@ Prerequisites C.LH, C.LHU, C.LBU::
 
 Operation (after expansion to 32-bit encodings)::
  See <<C.CLH>>, <<CLHU>>, <<CLBU>>, <<LH>>, <<LHU>>, <<LBU>>
-
-

src/insns/load_16bit_fp_dp.adoc

@@ -61,4 +61,3 @@ Prerequisites for C.FLD, C.FLDSP::
 
 Operation (after expansion to 32-bit encodings)::
  See <<FLD>>
-

src/insns/load_16bit_fp_sp.adoc

@@ -31,4 +31,3 @@ Prerequisites::
 
 Operation (after expansion to 32-bit encodings)::
  See <<FLW>>
-

src/insns/load_16bit_sprel.adoc

@@ -73,5 +73,3 @@ Prerequisites for C.LWSP::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CLW>>, <<CLD>>, <<LW>>, <<LD>>
-
-

src/insns/load_exceptions.adoc

@@ -22,4 +22,4 @@ listed below; in this case, _CHERI data fault_ is reported in the <<mtval>> or
 |==============================================================================
 
 :!load_res:
-:!has_cap_data:
+:!has_cap_data:

src/insns/new_encoding_note.adoc

@@ -1,4 +1,3 @@
 ifdef::cheri_v9_annotations[]
 NOTE: *CHERI v9 Note:* This page has *new* encodings.
 endif::[]
-

src/insns/sh4adduw_32bit.adoc

@@ -53,4 +53,3 @@ Legacy Mode Operation::
 --
 TBD
 --
-

src/insns/store_16bit.adoc

@@ -73,4 +73,3 @@ Prerequisites for C.SW::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CSD>>, <<CSW>>, <<SD>>, <<SW>>
-

src/insns/store_16bit_cap_sprel.adoc

@@ -37,4 +37,3 @@ Prerequisites::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CSC>>
-

src/insns/store_16bit_fp_dp.adoc

@@ -61,4 +61,3 @@ Prerequisites for C.FSD, C.FSDSP::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CFSD>>, <<FSD>>
-

src/insns/store_16bit_fp_sp.adoc

@@ -34,4 +34,3 @@ Prerequisites for C.FSW, C.FSWSP::
 
 Operation (after expansion to 32-bit encodings)::
  See <<FSW>>
-

src/insns/store_16bit_sprel.adoc

@@ -73,4 +73,3 @@ Prerequisites for C.SWSP::
 
 Operation (after expansion to 32-bit encodings)::
  See <<CSD>>, <<CSW>>, <<SD>>, <<SW>>
-

src/insns/wavedrom/c-cb-format-ls.adoc

@@ -10,4 +10,3 @@
   {bits: 3, name: 'funct3',type: 8, attr: ['3','C.BEQZ', 'C.BNEZ'],},
 ], config: {bits: 16}}
 ....
-

src/insns/wavedrom/c-ciw.adoc

@@ -9,4 +9,3 @@
   {bits: 3, name: 'funct3',type: 5, attr: ['3','cap: C.CINCOFFSET4CSPN=000','leg: C.ADDI4SPN=000']},
 ], config: {bits: 16}}
 ....
-

src/insns/wavedrom/c-cj-format-ls.adoc

@@ -6,6 +6,3 @@
   {bits: 3, name: 'funct3', type: 8, attr: ['3','cap: C.CJ=101','leg: C.J=101']},
 ], config: {bits: 16}}
 ....
-
-
-

src/insns/wavedrom/c-cjal-format-ls.adoc

@@ -6,6 +6,3 @@
   {bits: 3, name: 'funct3', type: 8, attr: ['3','cap rv32: C.CJAL=001','leg rv32: C.JAL=001']},
 ], config: {bits: 16}}
 ....
-
-
-

src/insns/wavedrom/c-cjalr-format-ls.adoc

@@ -9,4 +9,3 @@
   {bits: 4, name: 'funct4',  type: 8, attr: ['4', 'cap: C.CJALR=1001', 'leg: C.JALR=1001']},
 ], config: {bits: 16}}
 ....
-

src/insns/wavedrom/c-clc-clcsp.adoc

@@ -21,4 +21,3 @@
   {bits: 3, name: 'funct3', type: 8, attr: ['3','cap rv64: C.CLCSP=001']},
 ], config: {bits: 16}}
 ....
-

src/insns/wavedrom/c-cr-format-ls.adoc

@@ -9,4 +9,3 @@
   {bits: 4, name: 'funct4',  type: 8, attr: ['4','cap: C.CJR=1000', 'leg: C.JR=1000']},
 ], config: {bits: 16}}
 ....
-

src/insns/wavedrom/c-cs-format-ls.adoc

@@ -12,5 +12,3 @@
   {bits: 3, name: 'funct3',       type: 8, attr: ['3', 'cap: C.CSW=110', 'leg: C.SW=110', 'cap rv64: C.CSD=111', 'leg rv64: C.SD=111']},
 ], config: {bits: 16}}
 ....
-
-

src/insns/wavedrom/c-sp-load-css-dp-sprel.adoc

@@ -8,6 +8,3 @@
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg: C.FLDSP=001', 'cap rv32: C.CFLDSP=001']},
 ], config: {bits: 16}}
 ....
-
-
-

src/insns/wavedrom/c-sp-load-css-fp-sprel.adoc

@@ -8,6 +8,3 @@
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FLWSP=011']},
 ], config: {bits: 16}}
 ....
-
-
-

src/insns/wavedrom/c-sp-load-css-fp.adoc

@@ -9,4 +9,4 @@
   {bits: 3, name: 'imm',    types:3, attr: ['3', 'offset[5:3]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FLW=011']},
 ], config: {bits: 16}}
-....
+....

src/insns/wavedrom/c-sp-load-store-css.adoc

@@ -9,6 +9,3 @@
   {bits: 3, name: 'funct3',  type: 8, attr: ['3', 'cap rv64: C.CSDSP=111', 'leg rv64: C.SDSP=111', 'cap: C.CSWSP=110', 'leg: C.SWSP=110']},
 ], config: {bits: 16}}
 ....
-
-
-

src/insns/wavedrom/c-sp-load-store-fp.adoc

@@ -10,4 +10,4 @@
   {bits: 1, name: 'imm',    type: 1, attr: ['1','[5]']},
   {bits: 3, name: 'funct3', type: 3, attr: ['3', 'leg rv32: C.FLWSP=011']},
 ], config: {bits: 16}}
-....
+....

src/insns/wavedrom/c-sp-load-store.adoc

@@ -11,4 +11,4 @@
   {bits: 1, name: 'imm',    type: 1, attr: ['1','[5]']},
   {bits: 3, name: 'funct3', type: 3, attr: ['3', 'cap: C.CLWSP=010', 'leg: C.LWSP=010', 'cap rv64: C.CLDSP=011', 'leg rv64: C.LDSP=011']},
 ], config: {bits: 16}}
-....
+....

src/insns/wavedrom/c-sp-store-cap.adoc

@@ -18,4 +18,4 @@
   {bits: 3, name: 'imm',    types:3, attr: ['3', 'offset[5:3]','offset[5:4|8]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'cap rv32: C.CSC=111','cap rv64: C.CSC=101']},
 ], config: {bits: 16}}
-....
+....

src/insns/wavedrom/c-sp-store-css-fp-dp-sprel.adoc

@@ -9,6 +9,3 @@
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'int C.FSDSP=101', 'cap rv32: C.CFSDSP=101']},
 ], config: {bits: 16}}
 ....
-
-
-

src/insns/wavedrom/c-sp-store-css-fp-sprel.adoc

@@ -9,6 +9,3 @@
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FSWSP=111']},
 ], config: {bits: 16}}
 ....
-
-
-

src/insns/wavedrom/c-sp-store-css-fp.adoc

@@ -9,4 +9,4 @@
   {bits: 3, name: 'uimm',   types:3, attr: ['3', 'offset[5:3]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FSW=111']},
 ], config: {bits: 16}}
-....
+....

src/insns/wavedrom/c_mv.adoc

@@ -8,4 +8,4 @@
   {bits: 5, name: 'rd/cd',  type: 7, attr: ['5', 'dest!=0'],},
   {bits: 4, name: 'funct4', type: 8, attr: ['4', 'leg: C.MV=1000', 'cap: C.CMove=1000'],},
 ], config: {bits: 16}}
-....
+....

src/insns/wavedrom/cincoffset.adoc

@@ -21,4 +21,3 @@
   {bits: 12, name: 'imm',     attr: ['12','imm'], type: 4},
 ]}
 ....
-

src/insns/wavedrom/ct-unconditional.adoc

@@ -12,4 +12,3 @@
   {bits: 1,  name: '[20]',       attr: ['1'], type: 3},
 ], config:{fontsize: 12}}
 ....
-

src/insns/wavedrom/dret.adoc

@@ -10,4 +10,4 @@
   {bits: 5, name: 'rs1',      attr: ['5','0'],             type: 4},
   {bits: 12, name: 'funct12', attr: ['12','DRET=011110110010'], type: 8},
 ], config: {bits: 32}}
-....
+....

src/insns/wavedrom/fpload.adoc

@@ -9,6 +9,3 @@
   {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'],   type: 3},
 ]}
 ....
-
-
-

src/insns/wavedrom/fpstore.adoc

@@ -10,4 +10,3 @@
   {bits: 7,  name: 'imm[11:5]', attr: ['7','offset[11:5]'],   type: 3},
 ]}
 ....
-

src/insns/wavedrom/modeswitch_16bit.adoc

@@ -11,4 +11,3 @@
     { bits: 3, name: 0x4, attr: ['3', 'FUNCT3'] },
 ],config:{bits:16}}
 ....
-