clarify PTE fault exception priority, and add into instruction pages

src/cheri-pte-ext.adoc

@@ -100,7 +100,7 @@ If the CW bit is clear then:
 
 * When a capability load or AMO instruction is executed, the implementation
  clears the tag bit of the capability read from the virtual page.
-* When CRG is clear, the "no capability state", a store page fault exception
+* When CRG is clear, the "no capability state", a store/AMO page fault exception
  is raised when a capability store or AMO instruction is executed and the tag bit
  of the capability being written is set.
 * When CRG is set, the "pre-CW state", two schemes are permitted (also see <<section_hardware_pte_updates>>):
@@ -167,6 +167,13 @@ and the capability read from memory optionally has its tag set^1^.
 
 ^2^ See <<section_hardware_pte_updates>>.
 
+The exceptions added by {cheri_pte_ext_name}:
+
+* reuse the load page fault and store/AMO page fault exception cause values,
+and so the cause of the exception can be determined by software by checking bit zero of <<mtval2>>,
+<<stval2>> etc.
+* are all prioritized _above_ standard page fault exceptions.
+
 [#section_hardware_pte_updates]
 === Enabling Software or Hardware PTE updates
 

src/hypervisor-integration.adoc

@@ -75,7 +75,7 @@ part of {cheri_base_ext_name} when the hypervisor extension is supported. Its
 CSR address is 0x64b.
 
 <<htval2>> is updated following the same rules as <<mtval2>> for CHERI exceptions,
-load page fault and store page fault exceptions which are taken in HS-mode.
+load page fault and store/AMO page fault exceptions which are taken in HS-mode.
 
 The fields are identical to <<mtval2>> for CHERI exceptions.
 
@@ -196,7 +196,7 @@ include::img/vstdcreg.edn[]
 The <<vstval>> register is a VSXLEN-bit read-write register.
 
 <<vstval>> is updated following the same rules as <<mtval>> for CHERI exceptions,
-load page fault and store page faults which are taken in VS-mode.
+load page fault and store/AMO page faults which are taken in VS-mode.
 
 .Virtual supervisor trap value register
 [#vstval-format]

src/insns/load_exceptions.adoc

@@ -23,5 +23,10 @@ listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
 
 |==============================================================================
 +
+If {cheri_pte_ext_name} is implemented, and virtual memory is enabled, then the state of
+<<cheri_pte_ext,PTE>>.CW and <<cheri_pte_ext,PTE>>.CRG from the current virtual memory page,
+together with <<sstatusreg_pte,sstatus>>.CRG may cause a CHERI page fault exception.
+CHERI page fault exceptions are prioritized above standard page fault exceptions.
++
 :!load_res:
 :!has_cap_data:

src/insns/store_exceptions.adoc

@@ -22,5 +22,10 @@ listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
 | Bounds violation      | At least one byte accessed is outside the authority capability bounds, or the capability has <<section_cap_malformed,malformed>> bounds
 |==============================================================================
 +
+If {cheri_pte_ext_name} is implemented, and virtual memory is enabled, then the state of
+<<cheri_pte_ext,PTE>>.CW and <<cheri_pte_ext,PTE>>.CRG from the current virtual memory page may
+cause a CHERI page fault exception.
+CHERI page fault exceptions are prioritized above standard page fault exceptions.
++
 :!store_cond:
 :!has_cap_data:

src/riscv-integration.adoc

@@ -834,9 +834,9 @@ CHERI violations have the following order in priority:
 
 If a load page fault is caused by a CHERI <<cheri_pte_ext,PTE>> fault, then set bit zero of <<mtval2>> to 1 and all other bits to 0, otherwise set all bits to zero.
 
-===== mtval2 values for Store Page Faults
+===== mtval2 values for Store/AMO Page Faults
 
-If a store page fault is caused by a CHERI <<cheri_pte_ext,PTE>> fault, then set bit zero of <<mtval2>> to 1 and all other bits to 0, otherwise set all bits to zero.
+If a store/AMO page fault is caused by a CHERI <<cheri_pte_ext,PTE>> fault, then set bit zero of <<mtval2>> to 1 and all other bits to 0, otherwise set all bits to zero.
 
 [#supervisor-level-csrs-section]
 === Supervisor-Level CSRs
@@ -1051,7 +1051,7 @@ address is 0x14b.
 which are delegated to S-mode.
 
 The fields are identical to <<mtval2>> for CHERI exceptions, and for load and
-store page fault exceptions if {cheri_pte_ext_name} is implemented.
+store/AMO page fault exceptions if {cheri_pte_ext_name} is implemented.
 
 NOTE: <<stval2>> is not a standard RISC-V CSR, but <<mtval2>> is.