Rename AUIPCC, CJ* and J* instructions (#104)

Continued renaming of opcodes:
- Rename AUIPCC to AUIPC
- Rename CJ* to J* and JALR.PCC/JALR.CAP to JALR.MODE
- Fix minor issues in C.FSDSP/C.FSDSP introduced in previous commits

See #80

src/cap-description.adoc

@@ -205,7 +205,7 @@ capabilities are known as sealed entry (sentry) capabilities. A program may jump
 sentry capability to begin executing the instructions it references. The jump
 instruction automatically unseals the capability and installs it to the
 program counter capability (see
-xref:section_riscv_programmers_model[xrefstyle=short]). The <<CJALR>> instruction
+xref:section_riscv_programmers_model[xrefstyle=short]). The <<JALR>> instruction
 also seals the return address capability (if any) since it is the entry point
 to the caller function.
 

src/csv/CHERI_ISA.csv

@@ -5,14 +5,14 @@
 "C.SCSP","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","✔","","C2","","C.FSWSP","C.FSDSP","Store cap via cap, SP relative ","","","","","","","",""
 "C.LC","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","✔","","C0","","C.FLW","C.FLD","Load cap via cap","","","","","","","",""
 "C.SC","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","✔","","C0","","C.FSW","C.FSD","Store cap via cap ","","","","","","","",""
-"C.LWSP","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C2","","C.LWSP","C.LWSP","Load word via cap, SP relative","","","","","","","",""
-"C.SWSP","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C2","","C.SWSP","C.SWSP","Store word via cap, SP relative","","","","","","","",""
-"C.LW","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.LW","C.LW","Load word via cap","","","","","","","",""
-"C.SW","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.SW","C.SW","Store word via cap ","","","","","","","",""
-"C.LD","","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.LD","C.LD","Load word via cap","","","","","","","",""
-"C.SD","","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.SD","C.SD","Store word via cap ","","","","","","","",""
-"C.LDSP","","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.LDSP","C.LDSP","Load word via cap","","","","","","","",""
-"C.SDSP","","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.SDSP","C.SDSP","Store word via cap ","","","","","","","",""
+"C.LWSP","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C2","","C.LWSP","C.LWSP","Load word via cap, SP relative","","","","","","","",""
+"C.SWSP","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C2","","C.SWSP","C.SWSP","Store word via cap, SP relative","","","","","","","",""
+"C.LW","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.LW","C.LW","Load word via cap","","","","","","","",""
+"C.SW","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.SW","C.SW","Store word via cap ","","","","","","","",""
+"C.LD","","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.LD","C.LD","Load word via cap","","","","","","","",""
+"C.SD","","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.SD","C.SD","Store word via cap ","","","","","","","",""
+"C.LDSP","","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.LDSP","C.LDSP","Load word via cap","","","","","","","",""
+"C.SDSP","","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C0","","C.SDSP","C.SDSP","Store word via cap ","","","","","","","",""
 "LB","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","0","LOAD","","","","Load signed byte ","","","","","","","",""
 "LH","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","1","LOAD","","","","Load signed half ","","","","","","","",""
 "C.LH","✔","✔","","","","✔","✔","Both","","","","","✔","","","","","","","","","","","C0","","","","Load signed half ","","","","","","","",""
@@ -29,8 +29,7 @@
 "C.SH","✔","✔","","","","✔","✔","Both","","","","","✔","","","","","","","","","","","STORE","","","","Store half ","","","","","","","",""
 "SW","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","STORE","","","","Store word ","","","","","","","",""
 "SD","","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","STORE","","","","Store double ","","","","","","","",""
-"AUIPC","✔","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","AUIPC","","","","Add immediate to PCC address","","","","","","","",""
-"AUIPCC","✔","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","AUIPC","","AUIPC","AUIPC","Add immediate to PCC address, representability check","","","","","","","",""
+"AUIPC","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","AUIPC","","","","Add immediate to PCC address","","","","","","","",""
 "CINCOFFSET","✔","✔","","","","","✔","Both","","","","","","","","","","","","","","","","OP","R-type","","","Increment cap address by register, representability check","","","","","","","",""
 "CINCOFFSETIMM","✔","✔","","","","","✔","Both","","","","","","","","","","","","","","","","OP","I-type","","","Increment cap address by immediate, representability check","","","","","","","",""
 "CSETADDR","✔","✔","","","","","✔","Both","","","","","","","","","","","","","","","","OP","R-type","","","Replace capability address, representability check","","","","","","","",""
@@ -59,14 +58,13 @@
 "C.CINCOFFSET4CSPN","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C0","","C.ADDI4SPN","C.ADDI4SPN","ADD immediate to stack pointer, representability check","","","","","","","",""
 "C.MV","✔","✔","","","","✔","","Legacy","","","","✔","","","","","","","","","","","","C2","","","","Register Move","","","","","","","",""
 "C.CMOVE","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C2","","C.MV","C.MV","Same as CMove","","","","","","","",""
-"C.CJ","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C2","","C.J","C.J","Jump to PC+offset, bounds check minimum size target instruction","mode==D (optional)","","","","","","",""
-"C.CJAL","✔","","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C2","","C.JAL","C.JAL","Jump to PC+offset, bounds check minimum size target instruction, link to cd","mode==D (optional)","","","","","","",""
-"CJAL","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","JAL","","JAL","JAL","Jump to PC+offset, bounds check minimum size target instruction, link to cd","mode==D (optional)","","","","","","",""
-"JALR.CAP","✔","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","JALR","","JALR.PCC","JALR.PCC","CJALR available in legacy mode (with zero offset)","mode==D (optional)","","","","","","",""
-"JALR.PCC","✔","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","JALR","1-src 1-dst","","","RISC-V JALR available in capability modes (with zero offset)","mode==D (optional)","","","","","","",""
-"CJALR","✔","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","JALR","","JALR","JALR","Indirect cap jump and link, bounds check minimum size target instruction, unseal target cap, seal link cap","mode==D (optional)","","","","","","",""
-"C.CJALR","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C2","","C.JALR","C.JALR","Indirect cap jump and link, bounds check minimum size target instruction, unseal target cap, seal link cap","mode==D (optional)","","","","","","",""
-"C.CJR","✔","✔","","","","","✔","Capability","","","","✔","","","","","","","","","","","","C2","","C.JR","C.JR","Indirect cap jump, bounds check minimum size target instruction, unseal target cap","mode==D (optional)","","","","","","",""
+"C.J","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C2","","C.J","C.J","Jump to PC+offset, bounds check minimum size target instruction","mode==D (optional)","","","","","","",""
+"C.JAL","✔","","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C2","","C.JAL","C.JAL","Jump to PC+offset, bounds check minimum size target instruction, link to cd","mode==D (optional)","","","","","","",""
+"JAL","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","JAL","","JAL","JAL","Jump to PC+offset, bounds check minimum size target instruction, link to cd","mode==D (optional)","","","","","","",""
+"JALR.MODE","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","JALR","","JALR.PCC","JALR.PCC","JALR executes as in the other mode (with zero offset)","mode==D (optional)","","","","","","",""
+"JALR","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","JALR","","JALR","JALR","Indirect cap jump and link, bounds check minimum size target instruction, unseal target cap, seal link cap","mode==D (optional)","","","","","","",""
+"C.JALR","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C2","","C.JALR","C.JALR","Indirect cap jump and link, bounds check minimum size target instruction, unseal target cap, seal link cap","mode==D (optional)","","","","","","",""
+"C.JR","✔","✔","","","","✔","✔","Both","","","","✔","","","","","","","","","","","","C2","","C.JR","C.JR","Indirect cap jump, bounds check minimum size target instruction, unseal target cap","mode==D (optional)","","","","","","",""
 "DRET","✔","✔","✔","","","","","Legacy","","","","","","","","","","","","","","","","SYSTEM","","","","Return from debug mode, sets DDC from DDDC and PCC from DPCC","MODE<D","","","","","","",""
 "MRET","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","Return from machine mode handler, sets PCC from MTVECC, needs ASR permission","MODE<M","PCC.ASR==0","","","","","",""
 "SRET","✔","✔","✔","","","","","Both","","","","","","","","","","","","","","","","SYSTEM","","","","Return from supervisor mode handler, sets PCC from STVECC, needs ASR permission","MODE<S","PCC.ASR==0","mstatus.TSR==1 AND MODE==S","","","","",""

src/insns/auipcc_32bit.adoc → src/insns/auipc_32bit.adoc

@@ -3,16 +3,11 @@
 [#AUIPC,reftext="AUIPC"]
 ==== AUIPC
 
-See <<AUIPCC>>
-
-[#AUIPCC,reftext="AUIPCC"]
-==== AUIPCC
-
 Synopsis::
 Add upper immediate to *pc*/<<pcc>>
 
 Capability Mode Mnemonic::
-`auipcc cd, imm`
+`auipc cd, imm`
 
 Legacy Mode Mnemonic::
 `auipc rd, imm`
@@ -22,7 +17,7 @@ include::wavedrom/rv64_lui-auipc.adoc[]
 
 Capability Mode Description::
 Form a 32-bit offset from the 20-bit immediate filling the lowest 12 bits with
-zeros. Increment the address of the <<AUIPCC>> instruction's <<pcc>> by the
+zeros. Increment the address of the AUIPC instruction's <<pcc>> by the
 32-bit offset, then write the output capability to `cd`. The tag bit of the
 output capability is 0 if the incremented address is outside the <<pcc>>'s
 <<section_cap_representable_check>>.
@@ -34,13 +29,13 @@ the result in register `rd`.
 
 include::pcrel_debug_warning.adoc[]
 
-Prerequisites for AUIPCC::
+Prerequisites for Capability Mode::
 {cheri_base_ext_name}
 
-Prerequisites for AUIPC::
+Prerequisites for Legacy Mode::
 {cheri_legacy_ext_name}
 
-Operation for AUIPCC::
+Operation for AUIPC::
 +
 --
 TODO

src/insns/csetmode_32bit.adoc

@@ -1,6 +1,6 @@
 <<<
 
-[#csetmode]
+[#csetmode, reftext="CSETMODE"]
 ==== CSETMODE
 
 ifdef::cheri_v9_annotations[]

src/insns/cj_j_16bit.adoc → src/insns/j_16bit.adoc

@@ -1,47 +1,38 @@
 <<<
-//[#insns-cj_j-16bit,reftext="Conditional branches (C.CJ,C.J), 16-bit encodings"]
 
 [#C_J,reftext="C.J"]
 ==== C.J
 
-See <<C.CJ>>.
-
-[#C_CJ,reftext="C.CJ"]
-==== C.CJ
-
 Synopsis::
 Register based jumps without link, 16-bit encodings
 
-Capability Mode Mnemonic::
-`c.cj offset`
+Mnemonic::
+`c.j offset`
 
 Capability Mode Expansion::
-`cjal c0, offset`
-
-Legacy Mode Mnemonic::
-`c.j offset`
+`jal c0, offset`
 
 Legacy Mode Expansion::
 `jal x0, offset`
 
 Encoding::
-include::wavedrom/c-cj-format-ls.adoc[]
+include::wavedrom/c-j-format-ls.adoc[]
 
 Description::
 Set the next PC following the standard `jal` definition.
  Check a minimum length instruction is in <<pcc>> bounds at the target PC, take a CHERI Length Violation exception on error.
  *There is no difference in Capability Mode or Legacy Mode execution for this instruction.*
 
 Exceptions::
-See <<CJAL>>, <<JAL>>
+See <<JAL>>
 
 include::pcrel_debug_warning.adoc[]
 
-Prerequisites for C.CJ::
+Prerequisites for Capability Mode::
 {c_cheri_base_ext_names}
 
-Prerequisites for C.J::
+Prerequisites for Legacy Mode::
 {c_cheri_legacy_ext_names}
 
 Operation (after expansion to 32-bit encodings)::
- See <<CJAL>>, <<JAL>>
+ See <<JAL>>

src/insns/cjal_jal_16bit.adoc → src/insns/jal_16bit.adoc

@@ -1,22 +1,16 @@
 <<<
-//[#insns-cjal_jal-16bit,reftext="Conditional branches (C.CJAL,C.JAL), 16-bit encodings"]
 
 [#C_JAL,reftext="C.JAL"]
 ==== C.JAL
 
-See <<C.CJAL>>.
-
-[#C_CJAL,reftext="C.CJAL"]
-==== C.CJAL
-
 Synopsis::
 Register based jumps with link, 16-bit encodings
 
 Capability Mode Mnemonic (RV32)::
-`c.cjal c1, offset`
+`c.jal c1, offset`
 
 Capability Mode Expansion (RV32)::
-`cjal c1, offset`
+`jal c1, offset`
 
 Legacy Mode Mnemonic (RV32)::
 `c.jal x1, offset`
@@ -25,20 +19,20 @@ Legacy Mode Expansion (RV32)::
 `jal x1, offset`
 
 Encoding (RV32)::
-include::wavedrom/c-cjal-format-ls.adoc[]
+include::wavedrom/c-jal-format-ls.adoc[]
 
-include::cjal_jal_common.adoc[]
+include::jal_common.adoc[]
 
 Exceptions::
-See <<CJAL>>, <<JAL>>
+See <<JAL>>
 
 include::pcrel_debug_warning.adoc[]
 
-Prerequisites for C.CJAL::
+Prerequisites for Capability Mode::
 {c_cheri_base_ext_names}
 
-Prerequisites for C.JAL::
+Prerequisites for Legacy Mode::
 {c_cheri_legacy_ext_names}
 
 Operation (after expansion to 32-bit encodings)::
- See <<CJAL>>, <<JAL>>
+ See <<JAL>>

src/insns/cjal_jal_32bit.adoc → src/insns/jal_32bit.adoc

@@ -1,29 +1,18 @@
 <<<
-//[#insns-cjal_jal-32bit,reftext="Jumps (CJAL, JAL), 32-bit encodings"]
-
-[#CJ,reftext="CJ"]
-==== CJ
-
-Expands to <<CJAL>> following the expansion rule for <<J>> expanding to <<JAL>> from cite:[riscv-unpriv-spec].
 
 [#J,reftext="J"]
 ==== J
 
 Expands to <<JAL>> following the expansion rule from cite:[riscv-unpriv-spec].
 
-[#CJAL,reftext="CJAL"]
-==== CJAL
-
-See <<JAL>>
-
 [#JAL,reftext="JAL"]
-==== CJAL, JAL
+==== JAL
 
 Synopsis::
 Jump and link
 
 Capability Mode Mnemonic::
-`cjal cd, offset`
+`jal cd, offset`
 
 Legacy Mode Mnemonic::
 `jal rd, offset`
@@ -32,7 +21,7 @@ Encoding::
 include::wavedrom/ct-unconditional.adoc[]
 
 Capability Mode Description::
-CJAL's immediate encodes a signed offset in multiple of 2 bytes. The <<pcc>> is
+JAL's immediate encodes a signed offset in multiple of 2 bytes. The <<pcc>> is
 incremented by the sign-extended offset to form the jump target capability. The
 target capability is written to <<pcc>>. The <<pcc>> of the next instruction
 following the jump (<<pcc>> + 4) is sealed and written to `cd`.
@@ -49,19 +38,13 @@ address is not within the bounds of the <<pcc>>. In this case, _CHERI jump or
 branch fault_ is reported in the TYPE field and Length Violation is reported in
 the CAUSE field of <<mtval>> or <<stval>>.
 
-Prerequisites for CJAL::
+Prerequisites for Capability Mode::
 {cheri_base_ext_name}
 
-Prerequisites for JAL::
+Prerequisites for Legacy Mode::
 {cheri_legacy_ext_name}
 
-CJAL Operation::
-+
---
-TODO
---
-
-JAL Operation TODO #where's the target check?# ::
+Operation::
 +
 --
 TODO

src/insns/cjalr_jalr_16bit.adoc → src/insns/jalr_16bit.adoc

@@ -1,22 +1,16 @@
 <<<
-//[#insns-cjalr_jalr-16bit,reftext="Conditional branches (C.CJALR, C.JALR), 16-bit encodings"]
 
 [#C_JALR,reftext="C.JALR"]
 ==== C.JALR
 
-See <<C.CJALR>>.
-
-[#C_CJALR,reftext="C.CJALR"]
-==== C.CJALR
-
 Synopsis::
 Register based jumps with link, 16-bit encodings
 
 Capability Mode Mnemonic::
-`c.cjalr c1, cs1`
+`c.jalr c1, cs1`
 
 Capability Mode Expansion::
-`cjalr c1, 0(cs1)`
+`jalr c1, 0(cs1)`
 
 Legacy Mode Mnemonic::
 `c.jalr x1, rs1`
@@ -25,20 +19,20 @@ Legacy Mode Expansion::
 `jalr x1, 0(rs1)`
 
 Encoding::
-include::wavedrom/c-cjalr-format-ls.adoc[]
+include::wavedrom/c-jalr-format-ls.adoc[]
 
-include::cjalr_jalr_common.adoc[]
+include::jalr_common.adoc[]
 
 Exceptions::
-See <<CJALR>>, <<JALR>>
+See <<JALR>>
 
 include::pcrel_debug_warning.adoc[]
 
-Prerequisites C.CJALR::
+Prerequisites for Capability Mode::
 {c_cheri_base_ext_names}
 
-Prerequisites C.JALR::
+Prerequisites for Legacy Mode::
 {c_cheri_legacy_ext_names}
 
 Operation (after expansion to 32-bit encodings)::
- See <<CJALR>>, <<JALR>>
+ See <<JALR>>