Converging British English spellings to American English spellings (#454

)

This PR is for converging British English spellings to American English
spellings. This should close #453

src/cap-description.adoc

@@ -128,8 +128,8 @@ CLEN-bits is cleared.
 
 [#c_perm,reftext="C-permission"]
 Capability Permission \(C):: Allow reading capability data from memory if the
-authorising capability also grants <<r_perm>>. Allow writing capability data to
-memory if the authorising capability also grants <<w_perm>>.
+authorizing capability also grants <<r_perm>>. Allow writing capability data to
+memory if the authorizing capability also grants <<w_perm>>.
 
 [#x_perm,reftext="X-permission"]
 Execute Permission (X):: Allow instruction execution.
@@ -140,15 +140,15 @@ If a capability grants <<r_perm>> and <<c_perm>>, but no <<lm_perm>>, then a cap
 The rules specified by <<ACPERM>> are followed when <<w_perm>> and <<lm_perm>> are removed, so additional permissions may also be removed.
 Clearing a capability's <<lm_perm>> and <<w_perm>> allows sharing a read-only version of a data structure (e.g. a tree or linked list) without making a copy.
 
-NOTE: Implementations are allowed to retain invalid capability permissions loaded from memory instead of following the <<ACPERM>> behaviour of reducing them to _no permissions_.
+NOTE: Implementations are allowed to retain invalid capability permissions loaded from memory instead of following the <<ACPERM>> behavior of reducing them to _no permissions_.
 
 [#asr_perm,reftext="ASR-permission"]
 Access System Registers Permission (ASR):: Allow read and write access to all
 privileged (M-mode and S-mode) CSRs.
-If {tid_ext_name} is supported the <<utid>>, <<utidc>>, <<stid>>, <<stidc>>, <<mtid>>,
-<<mtidc>> registers are all considered privileged for the purposes of writing
-and unprivileged for reading, and thus require ASR-permission for writes but not reads.
-In all cases a suitable privilege mode is required for access.
+If {tid_ext_name} is supported the <<utid>>, <<utidc>>, <<vstid>>, <<vstidc>>, <<stid>>,
+<<stidc>>, <<mtid>>, <<mtidc>> registers are all considered privileged for the purposes
+of writing and unprivileged for reading, and thus require ASR-permission for writes but
+not reads. In all cases a suitable privilege mode is required for access.
 
 [#cap_permissions_encoding]
 ===== Permission Encoding
@@ -295,7 +295,7 @@ references if that SDP bit is set because it "owns" that object.
 
 ifdef::cheri_v9_annotations[]
 WARNING: *CHERI v9:* There is now a 1-bit otype (sentry or unsealed) and the old CHERI v9 otype no longer exists.
-The base CHERI-RISC-V standard does not have support for CHERI v9 CSEAL for sealed capabilities with object types and only has CSEALENTRY for sealed entry (sentry) capabilities.
+The base CHERI-RISC-V standard does not have support for CHERI v9 CSEAL for sealed capabilities with object types and only has <<SENTRY>> for sealed entry (sentry) capabilities.
 endif::[]
 
 This bit indicates the type of the capability: it is a sealed capability if the bit is 1 or unsealed if it is 0.
@@ -507,7 +507,7 @@ disambiguate the location of the bounds with respect to an out-of-bounds address
 R is calculated
 relative to the base by subtracting 2^MW-2^ from B.
 If B, T or _a_[E + MW - 1:E] is less than R, it is inferred that they lie in the
-2^E+MW^ aligned region above R labelled space~U~ in
+2^E+MW^ aligned region above R labeled space~U~ in
 xref:cap_bounds_map[xrefstyle=short] and the corrections _c~t~_ and _c~b~_ are
 computed accordingly. The overall effect is that the address can roam
 2^E+MW^/4 bytes below

src/cheri-pte-ext.adoc

@@ -87,7 +87,7 @@ include::img/sv48pte.edn[]
 [#sv57pte]
 include::img/sv57pte.edn[]
 
-NOTE: The behaviour in this section isn't relevant if:
+NOTE: The behavior in this section isn't relevant if:
 
 . The authorizing capability doesn't have <<c_perm>>, for loads, stores and AMOs.
 . {cheri_levels_ext_name} has cleared the stored tag, for stores and AMOs.
@@ -161,7 +161,7 @@ and the capability read from memory optionally has its tag set^1^.
 |===
 
 ^1^ The choice here is whether to take data dependent exceptions on loads or atomic operations.
- It is legal for the implementation to fault even if the tag is not set since this behaviour is only an optimization for software.
+ It is legal for the implementation to fault even if the tag is not set since this behavior is only an optimization for software.
  This means it is also legal to only check the tag under certain conditions and conservatively fault otherwise.
  Taking a trap when the tag is not set will introduce additional traps during revocation sweeps.
 

src/debug-integration.adoc

@@ -126,7 +126,7 @@ When leaving debug mode, the capability in <<dpcc>> is unsealed and written
 into <<pcc>>.  A debugger may write <<dpcc>> to change where the hart resumes
 and its mode, permissions, sealing or bounds.
 
-The legalisation of <<dpcc>> follows the same rules described for <<mepcc>>.
+The legalization of <<dpcc>> follows the same rules described for <<mepcc>>.
 
 [#dscratch0,reftext="dscratch0"]
 ==== Debug Scratch Register 0 (dscratch0)

src/hypervisor-integration.adoc

@@ -225,7 +225,7 @@ include::img/vstval2reg.edn[]
 The hypervisor extension defines several integer load and store instructions
 (such as <<HLV_W>>, <<HSV_W>> and <<HLVX_WU>>) that transfer the amount of integer data
 described in cite:[riscv-priv-spec] between the registers and memory as though
-V=1. These instructions change behaviour depending on the CHERI execution mode
+V=1. These instructions change behavior depending on the CHERI execution mode
 although the instruction's encoding remains unchanged.
 
 When in {cheri_cap_mode_name}, the hypervisor load and
@@ -234,7 +234,7 @@ xref:section_existing_riscv_insns[xrefstyle=short]. In
 {cheri_int_mode_name}, the instructions behave as
 described in cite:[riscv-priv-spec] and rely on an *x* register operand
 providing the effective address for the memory access; the capability
-authorising the memory access is <<ddc>>.
+authorizing the memory access is <<ddc>>.
 
 The exception cases remain as described in
 xref:section_existing_riscv_insns[xrefstyle=short] regardless of the CHERI
@@ -244,12 +244,12 @@ execution mode.
 
 Hypervisor virtual-machine load (<<HLV.C>>) and store (<<HSV.C>>) capability
 instructions read or write CLEN bits from memory as though V=1. These
-instructions change behaviour depending on the CHERI execution mode although
+instructions change behavior depending on the CHERI execution mode although
 the instruction's encoding remains unchanged.
 
 When in {cheri_cap_mode_name}, the hypervisor
 load and store capability instructions behave as described in
 xref:section_existing_riscv_insns[xrefstyle=short]. In
 {cheri_int_mode_name}, the instructions behave as rely
 on an *x* register operand providing the effective address for the memory
-access and the capability authorising the memory access is <<ddc>>.
+access and the capability authorizing the memory access is <<ddc>>.

src/insns/acperm_32bit.adoc

@@ -66,7 +66,7 @@ The rules from <<acperm_rules>> must be followed when removing permissions.
 
 ^1^ All the listed permissions in the set are either minimum or maximum.
 
-The behaviour of currently illegal combinations from <<acperm_rules>> is to clear the permission if invalid (or in the case of <<sl_perm>> set it to 0 (_local_)).
+The behavior of currently illegal combinations from <<acperm_rules>> is to clear the permission if invalid (or in the case of <<sl_perm>> set it to 0 (_local_)).
 
 * For RV64 all such combinations may be redefined by future extensions.
 * The RV32 only rules are added because they remove combinations which do not meet the encoding requirements for <<cap_perms_encoding32>>, or

src/insns/amo_32bit.adoc

@@ -29,12 +29,12 @@ Encoding::
 include::wavedrom/amo.adoc[]
 
 {cheri_cap_mode_name} Description::
-Standard atomic instructions, authorised by the capability in `cs1`.
+Standard atomic instructions, authorized by the capability in `cs1`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
-Standard atomic instructions, authorised by the capability in <<ddc>>.
+Standard atomic instructions, authorized by the capability in <<ddc>>.
 
 include::atomic_exceptions.adoc[]
 

src/insns/amoswap_32bit_cap.adoc

@@ -16,12 +16,12 @@ Encoding::
 include::wavedrom/amoswap_cap.adoc[]
 
 {cheri_cap_mode_name} Description::
-Atomic swap of capability type, authorised by the capability in `cs1`.
+Atomic swap of capability type, authorized by the capability in `cs1`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
-Atomic swap of capability type, authorised by the capability in <<ddc>>.
+Atomic swap of capability type, authorized by the capability in <<ddc>>.
 
 :cap_atomic:
 

src/insns/atomic_exceptions.adoc

@@ -2,7 +2,7 @@ Permissions::
 ifdef::cap_atomic[]
 Requires the authorizing capability to be tagged and not sealed.
 +
-Requires <<r_perm>> and <<w_perm>> in the authorising capability.
+Requires <<r_perm>> and <<w_perm>> in the authorizing capability.
 +
 If <<c_perm>> is not granted then store the memory tag as zero, and load `cd.tag` as zero.
 +
@@ -14,7 +14,7 @@ If `cd` is not sealed, this implicit <<ACPERM>> also clears <<el_perm>> to obtai
 The stored tag is also set to zero if the authorizing capability does not have <<sl_perm>> set but the stored data has a <<section_cap_level>> of 0 (see <<SC>>).
 endif::[]
 ifndef::cap_atomic[]
-Requires <<r_perm>> and <<w_perm>> in the authorising capability.
+Requires <<r_perm>> and <<w_perm>> in the authorizing capability.
 endif::[]
 +
 Requires all bytes of the access to be in capability bounds.

src/insns/cbo.clean.adoc

@@ -26,12 +26,12 @@ Encoding::
 
 {cheri_cap_mode_name} Description::
 A CBO.CLEAN instruction performs a clean operation on the cache block
-whose effective address is the base address specified in `cs1`. The authorising
+whose effective address is the base address specified in `cs1`. The authorizing
 capability for this operation is `cs1`.
 
 {cheri_int_mode_name} Description::
 A CBO.CLEAN instruction performs a clean operation on the cache block whose
-effective address is the base address specified in `rs1`. The authorising
+effective address is the base address specified in `rs1`. The authorizing
 capability for this operation is <<ddc>>.
 
 :cbo_clean_flush:

src/insns/cbo.flush.adoc

@@ -26,12 +26,12 @@ Encoding::
 
 {cheri_cap_mode_name} Description::
 A CBO.FLUSH instruction performs a flush operation on the cache block
-whose effective address is the base address specified in `cs1`. The authorising
+whose effective address is the base address specified in `cs1`. The authorizing
 capability for this operation is `cs1`.
 
 {cheri_int_mode_name} Description::
 A CBO.FLUSH instruction performs a flush operation on the cache block whose
-effective address is the base address specified in `rs1`. The authorising
+effective address is the base address specified in `rs1`. The authorizing
 capability for this operation is <<ddc>>.
 
 :cbo_clean_flush:

src/insns/cbo.inval.adoc

@@ -26,13 +26,13 @@ Encoding::
 
 {cheri_cap_mode_name} Description::
 A CBO.INVAL instruction performs an invalidate operation on the cache block
-whose effective address is the base address specified in `cs1`. The authorising
+whose effective address is the base address specified in `cs1`. The authorizing
 capability for this operation is `cs1`.
 
 {cheri_int_mode_name} Description::
 A CBO.INVAL instruction performs an invalidate operation on the cache block
 whose effective address is the base address specified in `rs1`. The
-authorising capability for this operation in <<ddc>>.
+authorizing capability for this operation in <<ddc>>.
 
 :cbo_inval:
 include::cbo_exceptions.adoc[]

src/insns/cbo.zero.adoc

@@ -29,15 +29,15 @@ A `cbo.zero` instruction performs stores of zeros to the full set of bytes
 corresponding to the cache block whose effective address is the base address
 specified in `cs1`. An implementation may or may not update the entire set of
 bytes atomically although each individual write must atomically clear the tag
-bit of the corresponding aligned CLEN-bit location. The authorising capability
+bit of the corresponding aligned CLEN-bit location. The authorizing capability
 for this operation is `cs1`.
 
 {cheri_int_mode_name} Description::
 A `cbo.zero` instruction performs stores of zeros to the full set of bytes
 corresponding to the cache block whose effective address is the base address
 specified in `cs1`. An implementation may or may not update the entire set of
 bytes atomically although each individual write must atomically clear the tag
-bit of the corresponding aligned CLEN-bit location. The authorising capability
+bit of the corresponding aligned CLEN-bit location. The authorizing capability
 for this operation is <<ddc>>.
 
 include::store_exceptions.adoc[]

src/insns/cbo_exceptions.adoc

@@ -1,5 +1,5 @@
 Exceptions::
-CHERI fault exceptions occur when the authorising capability fails one of the checks
+CHERI fault exceptions occur when the authorizing capability fails one of the checks
 listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
 <<stval2>> TYPE field and the corresponding code is written to CAUSE.
 +

src/insns/hypv-virt-load-cap.adoc

@@ -19,15 +19,15 @@ include::wavedrom/hypv-virt-load-cap.adoc[]
 Load a CLEN+1 bit value from memory as though V=1; i.e., with the address
 translation and protection, and endianness, that apply to memory accesses in
 either VS-mode or VU-mode. The effective address is the address of `cs1`. The
-authorising capability for the operation is `cs1`. A copy of the loaded value
+authorizing capability for the operation is `cs1`. A copy of the loaded value
 is written to `cd`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Load a CLEN+1 bit value from memory as though V=1; i.e., with the address
 translation and protection, and endianness, that apply to memory accesses in
-either VS-mode and VU-mode. The effective address is `rs1`. The authorising
+either VS-mode and VU-mode. The effective address is `rs1`. The authorizing
 capability for the operation is <<ddc>>. A copy of the loaded value is written
 to `cd`.
 

src/insns/hypv-virt-load.adoc

@@ -66,7 +66,7 @@ include::wavedrom/hypv-virt-load.adoc[]
 {cheri_cap_mode_name} Description::
 Performs a load as though V=1; i.e., with the address translation and
 protection, and endianness, that apply to memory accesses in either VS-mode or
-VU-mode. The effective address is the address of `cs1`. The authorising
+VU-mode. The effective address is the address of `cs1`. The authorizing
 capability for the operation is `cs1`. A copy of the loaded value is written to
 `rd`.
 +
@@ -75,7 +75,7 @@ include::load_store_c0.adoc[]
 {cheri_int_mode_name} Description::
 Performs a load as though V=1; i.e., with the address translation and
 protection, and endianness, that apply to memory accesses in either VS-mode or
-VU-mode. The effective address is the is `rs1`. The authorising capability for
+VU-mode. The effective address is the is `rs1`. The authorizing capability for
 the operation is <<ddc>>. A copy of the loaded value is written to `rd`.
 
 include::load_exceptions.adoc[]

src/insns/hypv-virt-loadx.adoc

@@ -27,7 +27,7 @@ Performs a load with the *execute* permission taking the place of *read*
 permission during address translation and as though V=1; i.e., with the address
 translation and protection, and endianness, that apply to memory access in
 either VS-mode or VU-mode. The effective address is the address of `cs1`. The
-authorising capability for the operation is `cs1`. A copy of the loaded value
+authorizing capability for the operation is `cs1`. A copy of the loaded value
 is written to `rd`.
 +
 include::load_store_c0.adoc[]
@@ -36,12 +36,12 @@ include::load_store_c0.adoc[]
 Performs a load with the *execute* permission taking the place of *read*
 permission during address translation and as though V=1; i.e., with the address
 translation and protection, and endianness, that apply to memory access in
-either VS-mode or VU-mode. The effective address is `rs1`. The authorising
+either VS-mode or VU-mode. The effective address is `rs1`. The authorizing
 capability for the operation is <<ddc>>. A copy of the loaded value is written
 to `rd`.
 
 Exceptions::
-CHERI fault exceptions occur when the authorising capability fails one of the checks
+CHERI fault exceptions occur when the authorizing capability fails one of the checks
 listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
 <<stval2>> TYPE field and the corresponding code is written to CAUSE.
 +

src/insns/hypv-virt-store-cap.adoc

@@ -19,15 +19,15 @@ include::wavedrom/hypv-virt-store-cap.adoc[]
 Store a CLEN+1 bit value in `cs2` to memory as though V=1; i.e., with the
 address translation and protection, and endianness, that apply to memory
 accesses in either VS-mode or VU-mode. The effective address is the address of
-`cs1`. The authorising capability for the operation is `cs1`.
+`cs1`. The authorizing capability for the operation is `cs1`.
 +
 include::load_store_c0.adoc[]
 
 {cheri_int_mode_name} Description::
 Store a CLEN+1 bit value in `cs2` to memory as though V=1; i.e., with the
 address translation and protection, and endianness, that apply to memory
 accesses in either VS-mode or VU-mode. The effective address is the `rs1`. The
-authorising capability for the operation is <<ddc>>.
+authorizing capability for the operation is <<ddc>>.
 
 include::store_tag_perms.adoc[]
 

src/insns/hypv-virt-store.adoc

@@ -51,7 +51,7 @@ include::wavedrom/hypv-virt-store.adoc[]
 {cheri_cap_mode_name} Description::
 Performs a store as though V=1; i.e., with the address translation and
 protection, and endianness, that apply to memory accesses in either VS-mode or
-VU-mode. The effective address is the address of `cs1`. The authorising
+VU-mode. The effective address is the address of `cs1`. The authorizing
 capability for the operation is `cs1`. A copy of `rs2` is written to memory at
 the location indicated by the effective address and the tag bit of each block
 of memory naturally aligned to CLEN/8 is cleared.
@@ -61,7 +61,7 @@ include::load_store_c0.adoc[]
 {cheri_int_mode_name} Description::
 Performs a store as though V=1; i.e., with address translation and protection,
 and endianness, that apply to memory accesses in either VS-mode or VU-mode. The
-effective address is `rs1`. The authorising capability for the operation is
+effective address is `rs1`. The authorizing capability for the operation is
 <<ddc>>. A copy of `rs2` is written to memory at the location indicated by the
 effective address and the tag bit of each block of memory naturally aligned to
 CLEN/8 is cleared.

src/insns/load_16bit.adoc

@@ -44,10 +44,10 @@ Encoding::
 include::wavedrom/reg-based-ldnstr.adoc[]
 
 {cheri_cap_mode_name} Description::
-Standard load instructions, authorised by the capability in `cs1`.
+Standard load instructions, authorized by the capability in `cs1`.
 
 {cheri_int_mode_name} Description::
-Standard load instructions, authorised by the capability in <<ddc>>.
+Standard load instructions, authorized by the capability in <<ddc>>.
 
 include::load_exceptions.adoc[]
 

src/insns/load_16bit_Zcb.adoc

@@ -41,10 +41,10 @@ Encoding::
 include::wavedrom/reg-based-ldnstr-Zcb.adoc[]
 
 {cheri_cap_mode_name} Description::
-Subword load instructions, authorised by the capability in `cs1`.
+Subword load instructions, authorized by the capability in `cs1`.
 
 {cheri_int_mode_name} Description::
-Subword load instructions, authorised by the capability in <<ddc>>.
+Subword load instructions, authorized by the capability in <<ddc>>.
 
 include::load_exceptions.adoc[]
 

src/insns/load_16bit_fp_dp.adoc

@@ -27,7 +27,7 @@ include::wavedrom/c-sp-load-css-dp.adoc[]
 include::wavedrom/c-sp-load-css-dp-sprel.adoc[]
 
 {cheri_int_mode_name} Description::
-Standard floating point stack pointer relative load instructions, authorised by the capability in <<ddc>>.
+Standard floating point stack pointer relative load instructions, authorized by the capability in <<ddc>>.
 
 NOTE: These instructions are available in RV64 {cheri_int_mode_name} only.
 In RV64 {cheri_cap_mode_name} they are remapped to <<C.LC>>/<<C.LCSP>>.

src/insns/load_16bit_fp_sp.adoc

@@ -22,7 +22,7 @@ include::wavedrom/c-sp-load-css-fp.adoc[]
 include::wavedrom/c-sp-load-css-fp-sprel.adoc[]
 
 {cheri_int_mode_name} Description::
-Standard floating point load instructions, authorised by the capability in <<ddc>>.
+Standard floating point load instructions, authorized by the capability in <<ddc>>.
 
 NOTE: These instructions are available in RV32 {cheri_int_mode_name} only.
 In {cheri_cap_mode_name} they are remapped to <<C.LC>>/<<C.LCSP>>.