Skip to content

Commit

Permalink
remove mstatus.CRG
Browse files Browse the repository at this point in the history
  • Loading branch information
tariqkurd-repo committed Nov 7, 2024
1 parent e26999e commit 62efaa3
Showing 1 changed file with 2 additions and 47 deletions.
49 changes: 2 additions & 47 deletions src/cheri-pte-ext.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -157,57 +157,12 @@ bit value of the capability read. This will introduce additional traps during re
a hardware updating mechanism.

[#xstatus_pte]
=== Extending the Machine (mstatus), Supervisor (sstatus) and Virtual Supervisor (vsstatus) Status Registers
=== Extending the Supervisor (sstatus) and Virtual Supervisor (vsstatus) Status Registers

The <<mstatusreg_pte,mstatus>>, <<sstatusreg_pte,sstatus>> and <<vsstatusreg_pte,vsstatus>> CSRs are extended to include the new Capability Read Generation (CRG) bit as shown.

<<mstatusreg_pte,mstatus>>.CRG is made visible in <<sstatusreg_pte,sstatus>>.CRG.
It is an SRW field, and so can be read and written from either Machine or Supervisor mode.
The <<sstatusreg_pte,sstatus>> and <<vsstatusreg_pte,vsstatus>> CSRs are extended to include the new Capability Read Generation (CRG) bit as shown.

When V=1 <<vsstatusreg_pte,vsstatus>>.CRG is in effect.

[#mstatusreg_pte]
.Machine-mode status (*mstatus*) register when MXLEN=64
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SPIE'},
{bits: 1, name: 'UBE'},
{bits: 1, name: 'MPIE'},
{bits: 1, name: 'SPP'},
{bits: 2, name: 'VS[1:0]'},
{bits: 2, name: 'MPP[1:0]'},
{bits: 2, name: 'FS[1:0]'},
{bits: 2, name: 'XS[1:0]'},
{bits: 1, name: 'MPRV'},
{bits: 1, name: 'SUM'},
{bits: 1, name: 'MXR'},
{bits: 1, name: 'TVM'},
{bits: 1, name: 'TW'},
{bits: 1, name: 'TSR'},
{bits: 1, name: 'SPELP'},
{bits: 1, name: 'SDT'},
{bits: 7, name: 'WPRI'},
{bits: 2, name: 'UXL[1:0]'},
{bits: 2, name: 'SXL[1:0]'},
{bits: 1, name: 'SBE'},
{bits: 1, name: 'MBE'},
{bits: 1, name: 'GVA'},
{bits: 1, name: 'MPV'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MPELP'},
{bits: 1, name: 'MDT'},
{bits: 19, name: 'WPRI'},
{bits: 1, name: 'CRG'},
{bits: 1, name: 'SD'},
], config:{lanes: 4, hspace:1024}}
....

[#sstatusreg_pte]
.Supervisor-mode status (*sstatus*) register when SXLEN=64
[wavedrom, ,svg]
Expand Down

0 comments on commit 62efaa3

Please sign in to comment.