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changed wording
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francislaus committed Jan 22, 2024
1 parent ce10ddd commit 60ebaab
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Showing 3 changed files with 6 additions and 6 deletions.
4 changes: 2 additions & 2 deletions src/insns/prefetch.i.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -38,8 +38,8 @@ likely to be accessed by an instruction fetch in the near future. The encoding
is only valid if imm[4:0]=0. The authorising capability for this operation is
`cs1`. This instruction does not throw any exceptions. However, following
<<CHERI_SPEC>>, this instruction does not perform a prefetch if it is
not authorized by `cs1`. This instruction does not issue a prefetch if one or
more of the following conditions of `cs1` are met:
not authorized by `cs1`. This instruction does not perform a memory access
if one or more of the following conditions of `cs1` are met:
* The tag is not set
* The sealed bit is set
* No bytes of the cache line requested is in bounds
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4 changes: 2 additions & 2 deletions src/insns/prefetch.r.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -38,8 +38,8 @@ likely to be accessed by a data read (i.e. load) in the near future. The
encoding is only valid if imm[4:0]=0. The authorising capability for this
operation is `cs1`. This instruction does not throw any exceptions. However,
in following <<CHERI_SPEC>>, this instruction does not perform a prefetch
if it is not authorized by `cs1`. This instruction does not issue a prefetch if one
or more of the following conditions of `cs1` are met:
if it is not authorized by `cs1`. This instruction does not perform a memory
access if one or more of the following conditions of `cs1` are met:
* The tag is not set
* The sealed bit is set
* No bytes of the cache line requested is in bounds
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4 changes: 2 additions & 2 deletions src/insns/prefetch.w.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -38,8 +38,8 @@ likely to be accessed by a data write (i.e. store) in the near future. The
encoding is only valid if imm[4:0]=0. The authorising capability for this
operation is `cs1`. This instruction does not throw any exceptions. However,
following <<CHERI_SPEC>>, this instruction does not perform a prefetch if it
is not authorized by `cs1`. This instruction does not issue a prefetch if one or
more of the following conditions of `cs1` are met:
is not authorized by `cs1`. This instruction does not perform a memory access
if one or more of the following conditions of `cs1` are met:
* The tag is not set
* The sealed bit is set
* No bytes of the cache line requested is in bounds
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