Fixed all of the FP <-> Int transfer types; added a test

arches/isa_json/olympia_uarch_rv64g.json

@@ -776,126 +776,126 @@
     {
         "mnemonic" : "fle.s",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "flt.s",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "feq.s",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fle.d",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "flt.d",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "feq.d",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fcvt.w.s",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fcvt.wu.s",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fcvt.l.s",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fcvt.lu.s",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fmv.x.w",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fclass.s",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fcvt.w.d",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fcvt.wu.d",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fcvt.l.d",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fcvt.lu.d",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fmv.x.d",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },
     {
         "mnemonic" : "fclass.d",
         "dispatch" : ["fpu"],
-        "pipe" : "i2f",
+        "pipe" : "f2i",
         "transfer" : true,
         "latency" : 2
     },

core/CoreUtils.hpp

@@ -23,8 +23,8 @@ namespace olympia::coreutils
     }
     inline core_types::RegFile determineRegisterFile(const mavis::OperandInfo::Element & reg)
     {
-        static const std::map<mavis::InstMetaData::OperandTypes, core_types::RegFile> mavis_optype_to_regfile = { 
-            // mapping of supported types ... 
+        static const std::map<mavis::InstMetaData::OperandTypes, core_types::RegFile> mavis_optype_to_regfile = {
+            // mapping of supported types ...
             {mavis::InstMetaData::OperandTypes::SINGLE, core_types::RegFile::RF_FLOAT},
             {mavis::InstMetaData::OperandTypes::DOUBLE, core_types::RegFile::RF_FLOAT},
             {mavis::InstMetaData::OperandTypes::WORD, core_types::RegFile::RF_INTEGER},
@@ -37,4 +37,5 @@ namespace olympia::coreutils
         sparta_assert(false, "Unknown reg type: " << static_cast<uint32_t>(reg.operand_type));
         return core_types::RegFile::RF_INVALID;
     }
+
 }

core/ExecutePipe.cpp

@@ -145,11 +145,25 @@ namespace olympia
         ILOG("Completing inst: " << ex_inst);
 
         // set scoreboard
-        if(SPARTA_EXPECT_FALSE(ex_inst->getPipe() == InstArchInfo::TargetPipe::I2F)) {
-            sparta_assert(reg_file_ == core_types::RegFile::RF_INTEGER,
-                          "Got an I2F instruction in an ExecutionPipe that does not source the integer RF");
-            const auto & dest_bits = ex_inst->getDestRegisterBitMask(core_types::RegFile::RF_FLOAT);
-            scoreboard_views_[core_types::RegFile::RF_FLOAT]->setReady(dest_bits);
+        if(SPARTA_EXPECT_FALSE(ex_inst->isTransfer()))
+        {
+            if(ex_inst->getPipe() == InstArchInfo::TargetPipe::I2F)
+            {
+                // Integer source -> FP dest -- need to mark the appropriate destination SB
+                sparta_assert(reg_file_ == core_types::RegFile::RF_INTEGER,
+                              "Got an I2F instruction in an ExecutionPipe that does not source the integer RF: " << ex_inst);
+                const auto & dest_bits = ex_inst->getDestRegisterBitMask(core_types::RegFile::RF_FLOAT);
+                scoreboard_views_[core_types::RegFile::RF_FLOAT]->setReady(dest_bits);
+            }
+            else {
+                // FP source -> Integer dest -- need to mark the appropriate destination SB
+                sparta_assert(ex_inst->getPipe() == InstArchInfo::TargetPipe::F2I,
+                              "Instruction is marked transfer type, but I2F nor F2I: " << ex_inst);
+                sparta_assert(reg_file_ == core_types::RegFile::RF_FLOAT,
+                              "Got an F2I instruction in an ExecutionPipe that does not source the Float RF: " << ex_inst);
+                const auto & dest_bits = ex_inst->getDestRegisterBitMask(core_types::RegFile::RF_INTEGER);
+                scoreboard_views_[core_types::RegFile::RF_INTEGER]->setReady(dest_bits);
+            }
         }
         else {
             const auto & dest_bits = ex_inst->getDestRegisterBitMask(reg_file_);

core/Inst.hpp

@@ -13,6 +13,7 @@
 
 #include "InstArchInfo.hpp"
 #include "CoreTypes.hpp"
+#include "MiscUtils.hpp"
 
 #include <cstdlib>
 #include <ostream>
@@ -100,6 +101,10 @@ namespace olympia
             opcode_info_    (opcode_info),
             inst_arch_info_ (inst_arch_info),
             is_store_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::STORE)),
+            is_transfer_(miscutils::isOneOf(inst_arch_info_->getTargetPipe(),
+                                            InstArchInfo::TargetPipe::I2F,
+                                            InstArchInfo::TargetPipe::F2I)),
+
             status_state_(Status::FETCHED)
         {
             sparta_assert(inst_arch_info_ != nullptr,
@@ -184,6 +189,7 @@ namespace olympia
 
         uint64_t    getRAdr() const        { return target_vaddr_ | 0x8000000; } // faked
         bool        isSpeculative() const  { return is_speculative_; }
+        bool        isTransfer() const     { return is_transfer_; }
 
         // Rename information
         core_types::RegisterBitMask & getSrcRegisterBitMask(const core_types::RegFile rf) {
@@ -220,7 +226,8 @@ namespace olympia
         uint64_t               unique_id_     = 0; // Supplied by Fetch
         uint64_t               program_id_    = 0; // Supplied by a trace Reader or execution backend
         bool                   is_speculative_ = false; // Is this instruction soon to be flushed?
-        bool                   is_store_ = false;
+        const bool             is_store_;
+        const bool             is_transfer_;  // Is this a transfer instruction (F2I/I2F)
         sparta::Scheduleable * ev_retire_    = nullptr;
         Status                 status_state_;
 
@@ -308,4 +315,4 @@ namespace olympia
     extern InstAllocator         inst_allocator;
     extern InstArchInfoAllocator inst_arch_info_allocator;
 
-}
+}

core/InstArchInfo.cpp

@@ -23,6 +23,7 @@ namespace olympia
         {"float",   InstArchInfo::TargetPipe::FLOAT},
         {"fmac",    InstArchInfo::TargetPipe::FMAC},
         {"i2f",     InstArchInfo::TargetPipe::I2F},
+        {"f2i",     InstArchInfo::TargetPipe::F2I},
         {"int",     InstArchInfo::TargetPipe::INT},
         {"lsu",     InstArchInfo::TargetPipe::LSU},
         {"mul",     InstArchInfo::TargetPipe::MUL},

core/InstArchInfo.hpp

@@ -54,6 +54,7 @@ namespace olympia
             FLOAT,
             FMAC,
             I2F,
+            F2I,
             INT,
             LSU,
             MUL,

core/MiscUtils.hpp

@@ -0,0 +1,14 @@
+// <MiscUtils.hpp> -*- C++ -*-
+
+#pragma once
+
+namespace olympia::miscutils
+{
+    // Is var in the set of vals
+    // https://stackoverflow.com/questions/15181579/c-most-efficient-way-to-compare-a-variable-to-multiple-values
+    // Usage: bool in = isOneOf(x, 1, 5, 7, 9, 23);
+    template<typename Var, typename ... Val>
+    bool isOneOf(Var&& var, Val&& ... val) {
+        return ((var == val) || ...);
+    }
+}

test/sim/CMakeLists.txt

@@ -51,6 +51,9 @@ sparta_named_test(olympia_coremark_test_report_html olympia -i 1M
 sparta_named_test(olympia_json_test_missing_opcodes olympia
   --workload json_tests/missing_opcodes.json)
 
+sparta_named_test(olympia_json_test_fp_transfers olympia
+  --workload json_tests/fp_transfers.json)
+
 # Test the arches
 file(GLOB TEST_YAML "${SIM_BASE}/arches/*.yaml")
 foreach(ARCH_FULL_PATH ${TEST_YAML})