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[vuop_gen] #238

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merged 6 commits into from
Dec 16, 2024
Merged

[vuop_gen] #238

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f8613ef
[vuop_gen]
orion160 Dec 8, 2024
64d9cf6
replace access to value in Optional
orion160 Dec 8, 2024
f9c8a80
[vuop_gen] move logic for viext
orion160 Dec 13, 2024
2fe674d
[vuop_gen] add assertion on allowed LMUL on widening & narrowing modes
orion160 Dec 13, 2024
7c48970
Unify tests
orion160 Dec 13, 2024
a6ea0be
Remove orphan inst_allocator from tests
orion160 Dec 13, 2024
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14 changes: 6 additions & 8 deletions arches/isa_json/gen_uarch_rv64v_json.py
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Original file line number Diff line number Diff line change
Expand Up @@ -51,14 +51,12 @@
"vwsub.wv" : {"pipe" : "vint", "uop_gen" : "WIDENING_MIXED", "latency" : 1},
"vwsub.wx" : {"pipe" : "vint", "uop_gen" : "WIDENING_MIXED", "latency" : 1},

# TODO: Vector Integer Arithmetic Instructions: Vector Integer Extension
# FIXME: Requires Mavis fix to support correctly
# "vzext.vf2" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1},
# "vsext.vf2" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1},
# "vzext.vf4" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1},
# "vsext.vf4" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1},
# "vzext.vf8" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1},
# "vsext.vf8" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1},
"vzext.vf2" : {"pipe" : "vint", "uop_gen" : "INT_EXT", "latency" : 1},
"vsext.vf2" : {"pipe" : "vint", "uop_gen" : "INT_EXT", "latency" : 1},
"vzext.vf4" : {"pipe" : "vint", "uop_gen" : "INT_EXT", "latency" : 1},
"vsext.vf4" : {"pipe" : "vint", "uop_gen" : "INT_EXT", "latency" : 1},
"vzext.vf8" : {"pipe" : "vint", "uop_gen" : "INT_EXT", "latency" : 1},
"vsext.vf8" : {"pipe" : "vint", "uop_gen" : "INT_EXT", "latency" : 1},

# Vector Integer Arithmetic Instructions: Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions
# FIXME: Requires Mavis fix to include vector mask
Expand Down
36 changes: 18 additions & 18 deletions arches/isa_json/olympia_uarch_rv64v.json
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Expand Up @@ -1735,21 +1735,21 @@
},
{
"mnemonic": "vsext.vf2",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vint",
"uop_gen": "INT_EXT",
"latency": 1
},
{
"mnemonic": "vsext.vf4",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vint",
"uop_gen": "INT_EXT",
"latency": 1
},
{
"mnemonic": "vsext.vf8",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vint",
"uop_gen": "INT_EXT",
"latency": 1
},
{
"mnemonic": "vslide1down.vx",
Expand Down Expand Up @@ -2209,20 +2209,20 @@
},
{
"mnemonic": "vzext.vf2",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vint",
"uop_gen": "INT_EXT",
"latency": 1
},
{
"mnemonic": "vzext.vf4",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vint",
"uop_gen": "INT_EXT",
"latency": 1
},
{
"mnemonic": "vzext.vf8",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vint",
"uop_gen": "INT_EXT",
"latency": 1
}
]
31 changes: 17 additions & 14 deletions core/Inst.hpp
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Expand Up @@ -18,6 +18,7 @@
#include "VectorConfig.hpp"
#include "MiscUtils.hpp"

#include <cstdint>
#include <cstdlib>
#include <ostream>
#include <unordered_map>
Expand Down Expand Up @@ -221,29 +222,34 @@ namespace olympia
}

const VectorConfigPtr getVectorConfig() const { return vector_config_; }

VectorConfigPtr getVectorConfig() { return vector_config_; }

void setTail(bool has_tail) { has_tail_ = has_tail; }

bool hasTail() const { return has_tail_; }

void setUOpParent(sparta::SpartaWeakPointer<olympia::Inst> & parent_uop)
{
parent_uop_ = parent_uop;
}

sparta::SpartaWeakPointer<olympia::Inst> getUOpParent() { return parent_uop_; }

// Branch instruction was taken (always set for JAL/JALR)
void setTakenBranch(bool taken) { is_taken_branch_ = taken; }

// Is this branch instruction mispredicted?
bool isMispredicted() const { return is_mispredicted_; }
void setMispredicted() { is_mispredicted_ = true; }
bool isMispredicted() const { return is_mispredicted_; }

void setMispredicted() { is_mispredicted_ = true; }

// TBD -- add branch prediction
void setSpeculative(bool spec) { is_speculative_ = spec; }

// Last instruction within the cache block fetched from the ICache
void setLastInFetchBlock(bool last) { last_in_fetch_block_ = last; }

bool isLastInFetchBlock() const { return last_in_fetch_block_; }

// Opcode information
Expand Down Expand Up @@ -271,25 +277,20 @@ namespace olympia
bool hasZeroRegSource() const
{
return std::any_of(getSourceOpInfoList().begin(), getSourceOpInfoList().end(),
[](const mavis::OperandInfo::Element & elem)
{
return elem.field_value == 0;
});
[](const mavis::OperandInfo::Element & elem)
{ return elem.field_value == 0; });
}

bool hasZeroRegDest() const
{
return std::any_of(getDestOpInfoList().begin(), getDestOpInfoList().end(),
[](const mavis::OperandInfo::Element & elem)
{
return elem.field_value == 0;
});
[](const mavis::OperandInfo::Element & elem)
{ return elem.field_value == 0; });
}

uint64_t getImmediate() const
{
sparta_assert(has_immediate_,
"Instruction does not have an immediate!");
sparta_assert(has_immediate_, "Instruction does not have an immediate!");
return opcode_info_->getImmediate();
}

Expand All @@ -298,7 +299,8 @@ namespace olympia
try
{
// If vm bit is 0, masking is enabled
const uint64_t vm_bit = opcode_info_->getSpecialField(mavis::OpcodeInfo::SpecialField::VM);
const uint64_t vm_bit =
opcode_info_->getSpecialField(mavis::OpcodeInfo::SpecialField::VM);
return vm_bit == 0;
}
catch (const mavis::UnsupportedExtractorSpecialFieldID & mavis_exception)
Expand Down Expand Up @@ -344,7 +346,8 @@ namespace olympia

bool isVector() const { return is_vector_; }

void setCoF(const bool &cof) { is_cof_ = cof; }
void setCoF(const bool & cof) { is_cof_ = cof; }

bool isCoF() const { return is_cof_; }

// Rename information
Expand Down
1 change: 1 addition & 0 deletions core/InstArchInfo.cpp
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Expand Up @@ -63,6 +63,7 @@ namespace olympia
{"NARROWING", InstArchInfo::UopGenType::NARROWING},
{"MAC", InstArchInfo::UopGenType::MAC},
{"MAC_WIDE", InstArchInfo::UopGenType::MAC_WIDE},
{"INT_EXT", InstArchInfo::UopGenType::INT_EXT},
{"NONE", InstArchInfo::UopGenType::NONE}
};

Expand Down
1 change: 1 addition & 0 deletions core/InstArchInfo.hpp
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Expand Up @@ -78,6 +78,7 @@ namespace olympia
NARROWING,
MAC,
MAC_WIDE,
INT_EXT,
NONE,
UNKNOWN
};
Expand Down
8 changes: 5 additions & 3 deletions core/InstGenerator.cpp
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Expand Up @@ -137,15 +137,17 @@ namespace olympia

if (jinst.find("vaddr") != jinst.end())
{
uint64_t vaddr = std::strtoull(jinst["vaddr"].get<std::string>().c_str(), nullptr, 0);
uint64_t vaddr =
std::strtoull(jinst["vaddr"].get<std::string>().c_str(), nullptr, 0);
inst->setTargetVAddr(vaddr);
}

VectorConfigPtr vector_config = inst->getVectorConfig();
if (jinst.find("vtype") != jinst.end())
{
// immediate, so decode from hex
uint64_t vtype = std::strtoull(jinst["vtype"].get<std::string>().c_str(), nullptr, 0);
uint64_t vtype =
std::strtoull(jinst["vtype"].get<std::string>().c_str(), nullptr, 0);
std::string binaryString = std::bitset<32>(vtype).to_string();
uint32_t sew = std::pow(2, std::stoi(binaryString.substr(26, 3), nullptr, 2)) * 8;
uint32_t lmul = std::pow(2, std::stoi(binaryString.substr(29, 3), nullptr, 2));
Expand All @@ -155,7 +157,7 @@ namespace olympia

if (jinst.find("vta") != jinst.end())
{
const bool vta = jinst["vta"].get<uint64_t>() > 0 ? true: false;
const bool vta = jinst["vta"].get<uint64_t>() > 0 ? true : false;
vector_config->setVTA(vta);
}

Expand Down
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