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VLSU Support #183

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Updating expected output
  • Loading branch information
aarongchan committed Aug 1, 2024
commit a8df2e818af69fcd34f4a091dcebf479b1bab8dc
28 changes: 14 additions & 14 deletions test/core/l2cache/expected_output/hit_case.out.EXPECTED
Original file line number Diff line number Diff line change
@@ -3,8 +3,8 @@
#Exe:
#SimulatorVersion:
#Repro:
#Start: Wednesday Wed Jul 31 23:16:07 2024
#Elapsed: 0.008922s
#Start: Thursday Thu Aug 1 00:01:05 2024
#Elapsed: 0.00775s
{0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295
{0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8
{0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8
@@ -28,16 +28,16 @@
{0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received
{0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent.
{0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE
{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef
{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef
{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_
{0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue
{0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31
{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' sinked
{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_
{0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32
{0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port
@@ -48,16 +48,16 @@
{0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU
{0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE
{0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU
{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef
{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef
{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef
{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue!
{0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache!
{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received
{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue!
{0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache!
{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received
@@ -77,15 +77,15 @@
{0000000053 00000053 top.dcache info} ReceiveAck_: Ack: '8' Received
{0000000053 00000053 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent.
{0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE
{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' 0
{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' vaddr: 0
{0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef
{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' 0
{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' vaddr: 0
{0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef
{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' 0
{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' vaddr: 0
{0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue!
{0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache!
{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received
{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' 0
{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' vaddr: 0
{0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue!
{0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache!
{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received
20 changes: 10 additions & 10 deletions test/core/l2cache/expected_output/single_access.out.EXPECTED
Original file line number Diff line number Diff line change
@@ -3,8 +3,8 @@
#Exe:
#SimulatorVersion:
#Repro:
#Start: Wednesday Wed Jul 31 23:16:02 2024
#Elapsed: 0.022853s
#Start: Thursday Thu Aug 1 00:01:16 2024
#Elapsed: 0.02575s
{0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295
{0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8
{0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8
@@ -28,16 +28,16 @@
{0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received
{0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent.
{0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE
{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef
{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef
{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_
{0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue
{0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31
{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' sinked
{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_
{0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32
{0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port
@@ -48,16 +48,16 @@
{0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU
{0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE
{0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU
{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef
{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef
{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef
{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue!
{0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache!
{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received
{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' 0
{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' vaddr: 0
{0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue!
{0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache!
{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received
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