Unit : L2Cache - linking misses to the same cacheline through next_re…

…q_ variable
riscv-software-src · Nov 21, 2023 · d99f35b · d99f35b
1 parent 3da074d
commit d99f35b
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Showing 3 changed files with 26 additions and 12 deletions.
diff --git a/core/MemoryAccessInfo.hpp b/core/MemoryAccessInfo.hpp
@@ -13,6 +13,11 @@ namespace olympia {
 
     class MemoryAccessInfoPairDef;
 
+    class MemoryAccessInfo;
+
+    using MemoryAccessInfoPtr       = sparta::SpartaSharedPointer<MemoryAccessInfo>;
+    using MemoryAccessInfoAllocator = sparta::SpartaSharedPointerAllocator<MemoryAccessInfo>;
+
     class MemoryAccessInfo {
     public:
 
@@ -88,6 +93,9 @@ namespace olympia {
         void setDestUnit(const ArchUnit & dest_unit) { dest_ = dest_unit; }
         const ArchUnit & getDestUnit() const { return dest_; }
 
+        void setNextReq(const MemoryAccessInfoPtr & nextReq) { next_req_ = nextReq; }
+        const MemoryAccessInfoPtr & getNextReq() { return next_req_; }
+
         MMUState getMMUState() const {
             return mmu_access_state_;
         }
@@ -125,6 +133,11 @@ namespace olympia {
         ArchUnit src_ = ArchUnit::NO_ACCESS;
         ArchUnit dest_ = ArchUnit::NO_ACCESS;
 
+        // Pointer to next request for DEBUG/TRACK
+        // (Note : Currently used only to track request with same cacheline in L2Cache 
+        // Not for functional/performance purpose)
+        MemoryAccessInfoPtr next_req_ = nullptr;
+
         // Scoreboards
         using ScoreboardViews = std::array<std::unique_ptr<sparta::ScoreboardView>, core_types::N_REGFILES>;
         ScoreboardViews scoreboard_views_;
@@ -153,7 +166,4 @@ namespace olympia {
                               SPARTA_ADDPAIR("cache", &MemoryAccessInfo::getCacheState),
                               SPARTA_FLATTEN(&MemoryAccessInfo::getInstPtr))
     };
-
-    using MemoryAccessInfoPtr       = sparta::SpartaSharedPointer<MemoryAccessInfo>;
-    using MemoryAccessInfoAllocator = sparta::SpartaSharedPointerAllocator<MemoryAccessInfo>;
 };
diff --git a/mss/L2Cache.cpp b/mss/L2Cache.cpp
@@ -461,14 +461,19 @@ namespace olympia_mss
             const auto req_cl = getCacheLine(req);
 
             auto is_cl_present = [&req, req_cl, getCacheLine] (auto reqPtr)
-                            { return (req != reqPtr && getCacheLine(reqPtr) == req_cl);};
+                            { return (req != reqPtr && getCacheLine(reqPtr) == req_cl); };
 
             // Send out the request to BIU for a cache MISS if it is not sent out already
-            auto reqIter = std::find_if(miss_pending_buffer_.begin(), miss_pending_buffer_.end(), is_cl_present);
+            auto reqIter = std::find_if(miss_pending_buffer_.rbegin(), miss_pending_buffer_.rend(), is_cl_present);
 
-            if (reqIter == miss_pending_buffer_.end()) {
+            if (reqIter == miss_pending_buffer_.rend()) {
                 sendOutReq_(req->getDestUnit(), req->getInstPtr());
             }
+            else {
+                // Found a request to same cacheLine.
+                // Link the current request to the last pending request
+                (*reqIter)->setNextReq(req);
+            }
         }
     }
 
@@ -617,7 +622,7 @@ namespace olympia_mss
     }
 
     // Cache lookup for a HIT or MISS on a given request
-    L2Cache::L2CacheState L2Cache::cacheLookup_(L2MemoryAccessInfoPtr mem_access_info_ptr) {
+    L2Cache::L2CacheState L2Cache::cacheLookup_(olympia::MemoryAccessInfoPtr mem_access_info_ptr) {
         const olympia::InstPtr & inst_ptr = mem_access_info_ptr->getInstPtr();
         uint64_t phyAddr = inst_ptr->getRAdr();
 

diff --git a/mss/L2Cache.hpp b/mss/L2Cache.hpp
@@ -190,19 +190,18 @@ namespace olympia_mss
             const uint32_t NO_ACCESS = 0;
         };
 
-        using L2MemoryAccessInfoPtr = sparta::SpartaSharedPointer<olympia::MemoryAccessInfo>;
         using L2ArchUnit = olympia::MemoryAccessInfo::ArchUnit;
         using L2CacheState = olympia::MemoryAccessInfo::CacheState;
-        using L2CachePipeline = sparta::Pipeline<L2MemoryAccessInfoPtr>;
+        using L2CachePipeline = sparta::Pipeline<olympia::MemoryAccessInfoPtr>;
 
         PipelineStages stages_;
         L2CachePipeline l2cache_pipeline_;
 
-        sparta::Queue<L2MemoryAccessInfoPtr> pipeline_req_queue_;
+        sparta::Queue<olympia::MemoryAccessInfoPtr> pipeline_req_queue_;
         const uint32_t pipeline_req_queue_size_;
         uint32_t inFlight_reqs_ = 0;
 
-        sparta::Buffer<L2MemoryAccessInfoPtr> miss_pending_buffer_;
+        sparta::Buffer<olympia::MemoryAccessInfoPtr> miss_pending_buffer_;
         const uint32_t miss_pending_buffer_size_;
 
 
@@ -223,7 +222,7 @@ namespace olympia_mss
         const bool is_dcache_connected_ = false;
 
         // allocator for this object type
-        sparta::SpartaSharedPointerAllocator<olympia::MemoryAccessInfo> & memory_access_allocator_;
+        olympia::MemoryAccessInfoAllocator & memory_access_allocator_;
         ////////////////////////////////////////////////////////////////////////////////
         // Event Handlers
         ////////////////////////////////////////////////////////////////////////////////