[Vector] Add test traces (#227)

riscv-software-src · Nov 28, 2024 · cb78046 · cb78046
1 parent c8685ae
commit cb78046
Show file tree

Hide file tree

Showing 10 changed files with 658 additions and 0 deletions.
diff --git a/test/core/vector/traces/add_vl256_e32_m1_ta.json b/test/core/vector/traces/add_vl256_e32_m1_ta.json
@@ -0,0 +1,43 @@
+[
+  {
+    "mnemonic": "vsetvli",
+    "vtype": "0x2",
+    "rd": 0,
+    "rs1": 13,
+    "vl": 256,
+    "vta": 1
+  },
+  {
+    "mnemonic": "vle32.v",
+    "vd": 0,
+    "rs1": 10,
+    "vaddr": "0xdaedbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vle32.v",
+    "vd": 1,
+    "rs1": 11,
+    "vaddr": "0xdaadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vadd.v",
+    "vd": 2,
+    "vs2": 0,
+    "vs1": 1
+  },
+  {
+    "mnemonic": "vse32.v",
+    "vs3": 2,
+    "rs1": 12,
+    "vaddr": "0xdeadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  }
+]
diff --git a/test/core/vector/traces/img_filter_vl256_e32_m1_ta.json b/test/core/vector/traces/img_filter_vl256_e32_m1_ta.json
@@ -0,0 +1,100 @@
+[
+  {
+    "mnemonic": "vsetvli",
+    "vtype": "0x2",
+    "rd": 0,
+    "rs1": 14,
+    "vl": 256,
+    "vta": 1
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 0,
+    "rs1": 13,
+    "imm": 0
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 1,
+    "rs1": 13,
+    "imm": 4
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 2,
+    "rs1": 13,
+    "imm": 8
+  },
+  {
+    "mnemonic": "vle32.v",
+    "vd": 0,
+    "rs1": 10,
+    "vaddr": "0xdaadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vle32.v",
+    "vd": 1,
+    "rs1": 11,
+    "vaddr": "0xdeadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vle32.v",
+    "vd": 2,
+    "rs1": 12,
+    "vaddr": "0xdaedbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vfmul.vf",
+    "vd": 0,
+    "vs2": 0,
+    "rs1": 0
+  },
+  {
+    "mnemonic": "vfmul.vf",
+    "vd": 1,
+    "vs2": 1,
+    "rs1": 1
+  },
+  {
+    "mnemonic": "vfmul.vf",
+    "vd": 1,
+    "vs2": 1,
+    "rs1": 1
+  },
+  {
+    "mnemonic": "vse32.v",
+    "vs3": 0,
+    "rs1": 10,
+    "vaddr": "0xdaadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vse32.v",
+    "vs3": 1,
+    "rs1": 11,
+    "vaddr": "0xdeadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vse32.v",
+    "vs3": 2,
+    "rs1": 12,
+    "vaddr": "0xdaedbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  }
+]
diff --git a/test/core/vector/traces/mma_e32_m1_vta.json b/test/core/vector/traces/mma_e32_m1_vta.json
@@ -0,0 +1,33 @@
+[
+  {
+    "mnemonic": "li",
+    "rs1": 10,
+    "imm": 32
+  },
+  {
+    "mnemonic": "vsetvli",
+    "rs1": 10,
+    "vtype": "0x10",
+    "rd": 0,
+    "vl": 32,
+    "vta": 1
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 15,
+    "rs1": 11,
+    "imm": 0
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 16,
+    "rs1": 17,
+    "imm": 0
+  },
+  {
+    "mnemonic": "vfmacc.vf",
+    "vd": 8,
+    "fs1": 15,
+    "vs1": 16
+  }
+]
diff --git a/test/core/vector/traces/mma_kernel_vl256_e32_m1_ta.json b/test/core/vector/traces/mma_kernel_vl256_e32_m1_ta.json
@@ -0,0 +1,133 @@
+[
+  {
+    "mnemonic": "li",
+    "rd": 12,
+    "imm": 128
+  },
+  {
+    "mnemonic": "vsetvli",
+    "vtype": "0x2",
+    "rd": 0,
+    "rs1": 12,
+    "vl": 256,
+    "vta": 0
+  },
+  {
+    "mnemonic": "vle32.v",
+    "vd": 8,
+    "rs1": 19,
+    "vaddr": "0xdeadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "ld",
+    "rd": 12,
+    "rs1": 8,
+    "imm": -144,
+    "vaddr": "0xdeedbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "vle32.v",
+    "vd": 0,
+    "rs1": 31,
+    "vaddr": "0xdaadbeef",
+    "mop": 0,
+    "eew": 32,
+    "stride": 32
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 15,
+    "rs1": 17,
+    "imm": 0
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 14,
+    "rs1": 5,
+    "imm": 0
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 13,
+    "rs1": 18,
+    "imm": 0
+  },
+  {
+    "mnemonic": "add",
+    "rd": 5,
+    "rs2": 17,
+    "rs1": 9
+  },
+  {
+    "mnemonic": "vfmacc.vf",
+    "vd": 8,
+    "rs1": 15,
+    "vs2": 0
+  },
+  {
+    "mnemonic": "vfmacc.vf",
+    "vd": 12,
+    "rs1": 14,
+    "vs2": 0
+  },
+  {
+    "mnemonic": "vfmacc.vf",
+    "vd": 16,
+    "rs1": 13,
+    "vs2": 0
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 15,
+    "rs1": 5,
+    "imm": 0
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 14,
+    "rs1": 16,
+    "imm": 0
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 13,
+    "rs1": 30,
+    "imm": 0
+  },
+  {
+    "mnemonic": "flw",
+    "fd": 12,
+    "rs1": 29,
+    "imm": 0
+  },
+  {
+    "mnemonic": "vfmacc.vf",
+    "vd": 20,
+    "rs1": 15,
+    "vs2": 0
+  },
+  {
+    "mnemonic": "vfmacc.vf",
+    "vd": 28,
+    "rs1": 14,
+    "vs2": 0
+  },
+  {
+    "mnemonic": "vfmacc.vf",
+    "vd": 4,
+    "rs1": 13,
+    "vs2": 0
+  },
+  {
+    "mnemonic": "vfmacc.vf",
+    "vd": 24,
+    "rs1": 12,
+    "vs2": 0
+  }
+]