Resolve conflicts between PR #152 and branch master (#211)

Signed-off-by: danbone <[email protected]> Co-authored-by: Daniel Bone <[email protected]> Co-authored-by: danbone <[email protected]>
riscv-software-src · Oct 31, 2024 · 8f9e442 · 8f9e442
1 parent 83dc12d
commit 8f9e442
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Showing 44 changed files with 2,026 additions and 711 deletions.
diff --git a/core/CMakeLists.txt b/core/CMakeLists.txt
@@ -3,6 +3,7 @@ add_library(core
   FusionDecode.cpp
   Core.cpp
   SimpleBranchPred.cpp
+  ICache.cpp
   Fetch.cpp
   Decode.cpp
   VectorUopGenerator.cpp

diff --git a/core/CPUFactories.hpp b/core/CPUFactories.hpp
@@ -5,6 +5,7 @@
 
 #include "sparta/simulation/ResourceFactory.hpp"
 #include "Core.hpp"
+#include "ICache.hpp"
 #include "Fetch.hpp"
 #include "Decode.hpp"
 #include "VectorUopGenerator.hpp"
@@ -40,6 +41,10 @@ namespace olympia{
         sparta::ResourceFactory<olympia::Core,
                                 olympia::Core::CoreParameterSet> core_rf;
 
+        //! \brief Resource Factory to build an Instruction Cache Unit
+        sparta::ResourceFactory<olympia::ICache,
+                olympia::ICache::ICacheParameterSet> icache_rf;
+
         //! \brief Resource Factory to build a Fetch Unit
         sparta::ResourceFactory<olympia::Fetch,
                                 olympia::Fetch::FetchParameterSet> fetch_rf;
@@ -61,7 +66,7 @@ namespace olympia{
         //! \brief Resource Factory to build a Execute Unit
         ExecuteFactory  execute_rf;
 
-        //! \brief Resource Factory to build a MMU Unit
+        //! \brief Resource Factory to build a Data Cache Unit
         sparta::ResourceFactory<olympia::DCache,
                 olympia::DCache::CacheParameterSet> dcache_rf;
 
@@ -104,7 +109,7 @@ namespace olympia{
         // //! \brief Resource Factory to build a IssueQueue Unit
         // sparta::ResourceFactory<olympia::IssueQueue,
         //                         olympia::IssueQueue::IssueQueueParameterSet> issue_queue_rf;
-                            
+
         //! \brief Set up the Mavis Decode functional unit
         MavisFactory  mavis_rf;
     }; // struct CPUFactories

diff --git a/core/CPUTopology.cpp b/core/CPUTopology.cpp
@@ -27,6 +27,14 @@ olympia::CoreTopologySimple::CoreTopologySimple(){
             sparta::TreeNode::GROUP_IDX_NONE,
             &factories->flushmanager_rf
         },
+        {
+            "icache",
+            "cpu.core*",
+            "Instruction Cache Unit",
+            sparta::TreeNode::GROUP_NAME_NONE,
+            sparta::TreeNode::GROUP_IDX_NONE,
+            &factories->icache_rf
+        },
         {
             "fetch",
             "cpu.core*",
@@ -160,6 +168,18 @@ olympia::CoreTopologySimple::CoreTopologySimple(){
 
     //! Instantiating ports of this topology
     port_connections = {
+        {
+            "cpu.core*.fetch.ports.out_fetch_icache_req",
+            "cpu.core*.icache.ports.in_fetch_req"
+        },
+        {
+            "cpu.core*.fetch.ports.in_icache_fetch_resp",
+            "cpu.core*.icache.ports.out_fetch_resp"
+        },
+        {
+            "cpu.core*.fetch.ports.in_icache_fetch_credits",
+            "cpu.core*.icache.ports.out_fetch_credit"
+        },
         {
             "cpu.core*.fetch.ports.out_fetch_queue_write",
             "cpu.core*.decode.ports.in_fetch_queue_write"
@@ -221,20 +241,32 @@ olympia::CoreTopologySimple::CoreTopologySimple(){
             "cpu.core*.l2cache.ports.in_dcache_l2cache_req"
         },
         {
-            "cpu.core*.dcache.ports.in_l2cache_ack",
-            "cpu.core*.l2cache.ports.out_l2cache_dcache_ack"
+            "cpu.core*.dcache.ports.in_l2cache_credits",
+            "cpu.core*.l2cache.ports.out_l2cache_dcache_credits"
         },
         {
             "cpu.core*.dcache.ports.in_l2cache_resp",
             "cpu.core*.l2cache.ports.out_l2cache_dcache_resp"
         },
+        {
+            "cpu.core*.icache.ports.out_l2cache_req",
+            "cpu.core*.l2cache.ports.in_icache_l2cache_req"
+        },
+        {
+            "cpu.core*.icache.ports.in_l2cache_credits",
+            "cpu.core*.l2cache.ports.out_l2cache_icache_credits"
+        },
+        {
+            "cpu.core*.icache.ports.in_l2cache_resp",
+            "cpu.core*.l2cache.ports.out_l2cache_icache_resp"
+        },
         {
             "cpu.core*.l2cache.ports.out_l2cache_biu_req",
             "cpu.core*.biu.ports.in_biu_req"
         },
         {
-            "cpu.core*.biu.ports.out_biu_ack",
-            "cpu.core*.l2cache.ports.in_biu_l2cache_ack"
+            "cpu.core*.biu.ports.out_biu_credits",
+            "cpu.core*.l2cache.ports.in_biu_l2cache_credits"
         },
         {
             "cpu.core*.biu.ports.out_biu_resp",

diff --git a/core/DCache.cpp b/core/DCache.cpp
@@ -22,8 +22,8 @@ namespace olympia
         in_l2cache_resp_.registerConsumerHandler(
             CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveRespFromL2Cache_, MemoryAccessInfoPtr));
 
-        in_l2cache_ack_.registerConsumerHandler(
-            CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveAckFromL2Cache_, uint32_t));
+        in_l2cache_credits_.registerConsumerHandler(
+            CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getCreditsFromL2Cache_, uint32_t));
 
         in_lsu_lookup_req_.registerConsumerEvent(in_l2_cache_resp_receive_event_);
         in_l2cache_resp_.registerConsumerEvent(in_l2_cache_resp_receive_event_);
@@ -291,14 +291,8 @@ namespace olympia
         in_l2_cache_resp_receive_event_.schedule();
     }
 
-    void DCache::receiveAckFromL2Cache_(const uint32_t & ack)
-    {
-        // When DCache sends the request to L2Cache for a miss,
-        // This bool will be set to false, and Dcache should wait for ack from
-        // L2Cache notifying DCache that there is space in it's dcache request buffer
-        //
-        // Set it to true so that the following misses from DCache can be sent out to L2Cache.
-        dcache_l2cache_credits_ = ack;
+    void DCache::getCreditsFromL2Cache_(const uint32_t &ack) {
+        dcache_l2cache_credits_ += ack;
     }
 
     // MSHR Entry allocation in case of miss

diff --git a/core/DCache.hpp b/core/DCache.hpp
@@ -1,5 +1,6 @@
 #pragma once
 
+#include "sparta/simulation/Unit.hpp"
 #include "sparta/ports/DataPort.hpp"
 #include "sparta/ports/SignalPort.hpp"
 #include "sparta/resources/Pipeline.hpp"
@@ -34,6 +35,16 @@ namespace olympia
         DCache(sparta::TreeNode* n, const CacheParameterSet* p);
 
       private:
+        bool dataLookup_(const MemoryAccessInfoPtr & mem_access_info_ptr);
+
+        void reloadCache_(uint64_t phy_addr);
+
+        void getInstsFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr);
+
+        void getCreditsFromL2Cache_(const uint32_t &);
+
+        void getRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr);
+
         ////////////////////////////////////////////////////////////////////////////////
         // L1 Data Cache Handling
         ////////////////////////////////////////////////////////////////////////////////
@@ -49,10 +60,6 @@ namespace olympia
 
         void setupL1Cache_(const CacheParameterSet* p);
 
-        bool dataLookup_(const MemoryAccessInfoPtr & mem_access_info_ptr);
-
-        void reloadCache_(uint64_t phy_addr);
-
         uint64_t getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr) const;
 
         using MSHREntryInfoPtr = sparta::SpartaSharedPointer<MSHREntryInfo>;
@@ -99,10 +106,10 @@ namespace olympia
         sparta::DataInPort<MemoryAccessInfoPtr> in_lsu_lookup_req_{&unit_port_set_,
                                                                    "in_lsu_lookup_req", 0};
 
-        sparta::DataInPort<uint32_t> in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1};
+        sparta::DataInPort<uint32_t> in_l2cache_credits_{&unit_port_set_, "in_l2cache_credits", 1};
 
-        sparta::DataInPort<MemoryAccessInfoPtr> in_l2cache_resp_{&unit_port_set_, "in_l2cache_resp",
-                                                                 1};
+        sparta::DataInPort<MemoryAccessInfoPtr> in_l2cache_resp_{&unit_port_set_,
+                                                                 "in_l2cache_resp", 1};
 
         ////////////////////////////////////////////////////////////////////////////////
         // Output Ports