Cleanup and documentation

riscv-software-src · Aug 5, 2024 · 5ab2f6b · 5ab2f6b
1 parent a0052f5
commit 5ab2f6b
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Showing 2 changed files with 16 additions and 4 deletions.
diff --git a/core/VLSU.cpp b/core/VLSU.cpp
@@ -198,13 +198,15 @@ namespace olympia
             {
                 // TODO: Address Unroller Class
                 sparta::memory::addr_t addr = inst_ptr->getTargetVAddr();
+                // Need to modify for indexed load/stores
                 inst_ptr->setTargetVAddr(addr + inst_ptr->getStride());
                 LoadStoreInstInfoPtr load_store_info_ptr = createLoadStoreInst_(inst_ptr);
                 load_store_info_ptr->getMemoryAccessInfoPtr()->setVAddr(inst_ptr->getTargetVAddr());
                 const LoadStoreInstIterator & iter =
                     mem_request_queue_.push_back(load_store_info_ptr);
                 load_store_info_ptr->setIssueQueueIterator(iter);
                 uint32_t vector_iter = inst_ptr->getCurrVLSUIters();
+                // setting current vlsu iteration
                 inst_ptr->setCurrVLSUIters(++vector_iter);
                 load_store_info_ptr->setVLSUStatusState(Inst::Status::DISPATCHED);
                 handleOperandIssueCheck_(load_store_info_ptr);
@@ -697,6 +699,10 @@ namespace olympia
     // Retire load/store instruction
     void VLSU::completeInst_()
     {
+        // For VLSU, the condition for completing an instruction
+        // is for all memory requests are done.
+        // Once done we then pop it from inst_queue as well and send to ROB for retiring
+
         // Check if flushing event occurred just now
         if (!ldst_pipeline_.isValid(complete_stage_))
         {
@@ -715,9 +721,12 @@ namespace olympia
         }
         else
         {
+            // Don't complete inst until we get the last memory request
+            // For stores, we have to wait for handleCacheLookupReq_ to mark as RETIRED
+            // For loads we don't wait for that to process it, so we don't gate on that condition
             if (inst_ptr->getCurrVLSUIters() >= total_iters && load_store_info_ptr->isLastMemOp()
-                && load_store_info_ptr->getVLSUStatusState() != Inst::Status::COMPLETED
-                && !(load_store_info_ptr->isRetired()))
+                && (load_store_info_ptr->getVLSUStatusState() == Inst::Status::RETIRED
+                    || !inst_ptr->isStoreInst()))
             {
                 const bool is_store_inst = inst_ptr->isStoreInst();
                 ILOG("Completing inst: " << inst_ptr);

diff --git a/core/VLSU.hpp b/core/VLSU.hpp
@@ -53,7 +53,7 @@ namespace olympia
             PARAMETER(uint32_t, replay_issue_delay, 3, "Replay Issue delay")
             // VLSU microarchitecture parameters
             PARAMETER(
-                bool, allow_speculative_load_exec, false,
+                bool, allow_speculative_load_exec, true,
                 "Allow loads to proceed speculatively before all older store addresses are known")
             // Pipeline length
             PARAMETER(uint32_t, mmu_lookup_stage_length, 1, "Length of the mmu lookup stage")
@@ -133,8 +133,11 @@ namespace olympia
 
         // Issue Queue
         using LoadStoreIssueQueue = sparta::Buffer<LoadStoreInstInfoPtr>;
+        // holds loadstoreinfo memory requests
         LoadStoreIssueQueue mem_request_queue_;
-        InstQueue inst_queue_; // holds inst_ptrs until done
+        // holds inst_ptrs until done
+        // one instruction can have multiple memory requests
+        InstQueue inst_queue_;
         const uint32_t mem_request_queue_size_;
         const uint32_t inst_queue_size_;