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Update IOM_020 non-normative text on number of IOMMU #44

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Jun 4, 2024
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Update IOM_020 non-normative text on number of IOMMU #44

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6 changes: 4 additions & 2 deletions src/server_soc_requirements.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -93,7 +93,6 @@ deliver external interrupts to the RISC-V application processor harts.
| ID# ^| Requirement
| IOM_010 | All IOMMUs in the SoC MUST support the RISC-V IOMMU specification
cite:[IOMMU].
2+| _The number of IOMMUs implemented in the SoC is `UNSPECIFIED`._

| IOM_020 a| All DMA capable peripherals (RCiEP and non-PCIe devices) and all
PCIe root ports accessible by software on the RISC-V application
Expand All @@ -112,7 +111,10 @@ deliver external interrupts to the RISC-V application processor harts.
restrict DMA originating from such devices to a subset of memory to enhance
security and software fault tolerance. The address translation capability
provided by the IOMMU enables usages such as passthrough of such devices to
virtual machines, shared virtual addressing, etc._
virtual machines, shared virtual addressing, etc._ +
+
_The number of IOMMUs implemented in the SoC to satisfy requirement IOM_020
is `UNSPECIFIED`._

| IOM_030 | The IOMMU governing a PCIe root port MUST support at least 16-bit
wide device IDs.
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