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add rs, w0s, w1s, ws and wos bit field types
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inst u_bit_field: rggen_bit_field #( | ||
WIDTH: <%= width %>, | ||
INITIAL_VALUE: <%= initial_value %>, | ||
SW_READ_ACTION: rggen_sw_action::<%= read_action %>, | ||
SW_WRITE_ACTION: rggen_sw_action::<%= write_action %> | ||
)( | ||
i_clk: <%= clock %>, | ||
i_rst: <%= reset %>, | ||
bit_field_if: <%= bit_field_if %>, | ||
o_write_trigger: _, | ||
o_read_trigger: _, | ||
i_sw_write_enable: <%= sw_write_enable %>, | ||
i_hw_write_enable: '0, | ||
i_hw_write_data: '0, | ||
i_hw_set: '0, | ||
i_hw_clear: <%= clear[loop_variables] %>, | ||
i_value: '0, | ||
i_mask: '1, | ||
o_value: <%= value_out[loop_variables] %>, | ||
o_value_unmasked: _ | ||
); |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,36 @@ | ||
# frozen_string_literal: true | ||
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RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do | ||
veryl do | ||
build do | ||
input :clear, { | ||
name: "i_#{full_name}_clear", | ||
width: width, array_size: array_size | ||
} | ||
output :value_out, { | ||
name: "o_#{full_name}", | ||
width: width, array_size: array_size | ||
} | ||
end | ||
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main_code :bit_field, from_template: true | ||
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private | ||
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def read_action | ||
{ | ||
rs: 'READ_SET', wos: 'READ_NONE' | ||
}.fetch(bit_field.type, 'READ_DEFAULT') | ||
end | ||
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def write_action | ||
{ | ||
rs: 'WRITE_NONE', w0s: 'WRITE_0_SET', w1s: 'WRITE_1_SET' | ||
}.fetch(bit_field.type, 'WRITE_SET') | ||
end | ||
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def sw_write_enable | ||
bit_field.writable? && all_bits_1 || all_bits_0 | ||
end | ||
end | ||
end |
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