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add rs, w0s, w1s, ws and wos bit field types
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taichi-ishitani committed Nov 20, 2024
1 parent a35c2be commit d23cc16
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Showing 8 changed files with 2,123 additions and 0 deletions.
1 change: 1 addition & 0 deletions lib/rggen/veryl.rb
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Expand Up @@ -29,6 +29,7 @@
'veryl/bit_field/type/rohw',
'veryl/bit_field/type/row0trg_row1trg',
'veryl/bit_field/type/rowo_rowotrg',
'veryl/bit_field/type/rs_w0s_w1s_ws_wos',
'veryl/bit_field/type/rw_rwtrg_w1',
'veryl/bit_field/veryl_top',
'veryl/register/veryl_top',
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21 changes: 21 additions & 0 deletions lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.erb
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inst u_bit_field: rggen_bit_field #(
WIDTH: <%= width %>,
INITIAL_VALUE: <%= initial_value %>,
SW_READ_ACTION: rggen_sw_action::<%= read_action %>,
SW_WRITE_ACTION: rggen_sw_action::<%= write_action %>
)(
i_clk: <%= clock %>,
i_rst: <%= reset %>,
bit_field_if: <%= bit_field_if %>,
o_write_trigger: _,
o_read_trigger: _,
i_sw_write_enable: <%= sw_write_enable %>,
i_hw_write_enable: '0,
i_hw_write_data: '0,
i_hw_set: '0,
i_hw_clear: <%= clear[loop_variables] %>,
i_value: '0,
i_mask: '1,
o_value: <%= value_out[loop_variables] %>,
o_value_unmasked: _
);
36 changes: 36 additions & 0 deletions lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.rb
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# frozen_string_literal: true

RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
veryl do
build do
input :clear, {
name: "i_#{full_name}_clear",
width: width, array_size: array_size
}
output :value_out, {
name: "o_#{full_name}",
width: width, array_size: array_size
}
end

main_code :bit_field, from_template: true

private

def read_action
{
rs: 'READ_SET', wos: 'READ_NONE'
}.fetch(bit_field.type, 'READ_DEFAULT')
end

def write_action
{
rs: 'WRITE_NONE', w0s: 'WRITE_0_SET', w1s: 'WRITE_1_SET'
}.fetch(bit_field.type, 'WRITE_SET')
end

def sw_write_enable
bit_field.writable? && all_bits_1 || all_bits_0
end
end
end
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