Release v2.1.1

renesas · Nov 10, 2020 · 9b01a0e · 9b01a0e
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diff --git a/README.md b/README.md
@@ -20,6 +20,7 @@ Download the latest FSP version from the [Releases page](https://github.com/rene
 - EK-RA6M3
 - EK-RA6M3G
 - EK-RA6M4
+- RSSK-RA6T1
 
 ### Setup Instructions
 

diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h
@@ -44,16 +44,16 @@
 #define FSP_VERSION_MINOR (1U)
 
 /** FSP pack patch version. */
-#define FSP_VERSION_PATCH (0U)
+#define FSP_VERSION_PATCH (1U)
 
 /** FSP pack version build number (currently unused). */
 #define FSP_VERSION_BUILD           (0U)
 
 /** Public FSP version name. */
-#define FSP_VERSION_STRING          ("2.1.0")
+#define FSP_VERSION_STRING          ("2.1.1")
 
 /** Unique FSP version ID. */
-#define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 2.1.0")
+#define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 2.1.1")
 
 /**********************************************************************************************************************
  * Typedef definitions

diff --git a/ra/fsp/inc/instances/r_agt.h b/ra/fsp/inc/instances/r_agt.h
@@ -59,7 +59,8 @@ typedef enum e_agt_clock
 {
     AGT_CLOCK_PCLKB          = 0x00,   ///< PCLKB count source, division by 1, 2, or 8 allowed
     AGT_CLOCK_LOCO           = 0x40,   ///< LOCO count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed
-    AGT_CLOCK_AGT0_UNDERFLOW = 0x50,   ///< Underflow event signal from AGT0, division must be 1
+    AGT_CLOCK_AGT_UNDERFLOW  = 0x50,   ///< Underflow event signal from next lowest AGT channel, division must be 1
+    AGT_CLOCK_AGT0_UNDERFLOW = 0x50,   // Underflow event signal from AGT0, division must be 1 (deprecated)
     AGT_CLOCK_SUBCLOCK       = 0x60,   ///< Subclock count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed
     AGT_CLOCK_P402           = 0x92,   ///< Counts events on P402, events are counted in deep software standby mode
     AGT_CLOCK_P403           = 0x93,   ///< Counts events on P403, events are counted in deep software standby mode

diff --git a/ra/fsp/lib/r_ble/cm4_ac6/all/libr_ble.a b/ra/fsp/lib/r_ble/cm4_ac6/all/libr_ble.a
diff --git a/ra/fsp/lib/r_ble/cm4_ac6/all_freertos/libr_ble.a b/ra/fsp/lib/r_ble/cm4_ac6/all_freertos/libr_ble.a
diff --git a/ra/fsp/lib/r_ble/cm4_gcc/all/libr_ble.a b/ra/fsp/lib/r_ble/cm4_gcc/all/libr_ble.a
diff --git a/ra/fsp/lib/r_ble/cm4_gcc/all_freertos/libr_ble.a b/ra/fsp/lib/r_ble/cm4_gcc/all_freertos/libr_ble.a
diff --git a/ra/fsp/lib/r_ble/cm4_iar/all/libr_ble.a b/ra/fsp/lib/r_ble/cm4_iar/all/libr_ble.a
diff --git a/ra/fsp/lib/r_ble/cm4_iar/all_freertos/libr_ble.a b/ra/fsp/lib/r_ble/cm4_iar/all_freertos/libr_ble.a
diff --git a/ra/fsp/lib/rm_motor_current/cm4_ac6/librm_motor_current.a b/ra/fsp/lib/rm_motor_current/cm4_ac6/librm_motor_current.a
diff --git a/ra/fsp/lib/rm_motor_current/cm4_gcc/librm_motor_current.a b/ra/fsp/lib/rm_motor_current/cm4_gcc/librm_motor_current.a
diff --git a/ra/fsp/lib/rm_motor_current/cm4_iar/librm_motor_current.a b/ra/fsp/lib/rm_motor_current/cm4_iar/librm_motor_current.a
diff --git a/ra/fsp/lib/rm_motor_estimate/cm4_ac6/librm_motor_estimate.a b/ra/fsp/lib/rm_motor_estimate/cm4_ac6/librm_motor_estimate.a
diff --git a/ra/fsp/lib/rm_motor_estimate/cm4_gcc/librm_motor_estimate.a b/ra/fsp/lib/rm_motor_estimate/cm4_gcc/librm_motor_estimate.a
diff --git a/ra/fsp/lib/rm_motor_estimate/cm4_iar/librm_motor_estimate.a b/ra/fsp/lib/rm_motor_estimate/cm4_iar/librm_motor_estimate.a
diff --git a/ra/fsp/lib/rm_motor_speed/cm4_ac6/librm_motor_speed.a b/ra/fsp/lib/rm_motor_speed/cm4_ac6/librm_motor_speed.a
diff --git a/ra/fsp/lib/rm_motor_speed/cm4_gcc/librm_motor_speed.a b/ra/fsp/lib/rm_motor_speed/cm4_gcc/librm_motor_speed.a
diff --git a/ra/fsp/lib/rm_motor_speed/cm4_iar/librm_motor_speed.a b/ra/fsp/lib/rm_motor_speed/cm4_iar/librm_motor_speed.a
diff --git a/ra/fsp/src/bsp/mcu/all/bsp_security.c b/ra/fsp/src/bsp/mcu/all/bsp_security.c
@@ -68,7 +68,7 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void);
 
 /* &__tz_<REGION>_N is the start address of the non-secure region. */
 BSP_DONT_REMOVE void const * const __tz_FLASH_C      BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start" = 0;
-BSP_DONT_REMOVE void const * const __tz_FLASH_N      BSP_ALIGN_VARIABLE(32768) @".tz_flash_ns_start";
+BSP_DONT_REMOVE void const * const __tz_FLASH_N      BSP_ALIGN_VARIABLE(32768) @".tz_flash_ns_start" = 0;
 BSP_DONT_REMOVE void const * const __tz_RAM_C        BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start";
 BSP_DONT_REMOVE void const * const __tz_RAM_N        BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start";
 BSP_DONT_REMOVE void const * const __tz_DATA_FLASH_N BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start";

diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h
@@ -76,6 +76,7 @@
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                   (1U)
 
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                (0x03)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                   (1)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                       (1)
 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM           (1U)

diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h
@@ -76,6 +76,7 @@
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                   (1U)
 
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                (0x03)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                   (1)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                       (1)
 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM           (1U)

diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h
@@ -76,6 +76,7 @@
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                   (1U)
 
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                (0x03)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                   (1)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                       (1U)
 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM           (1U)

diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h
@@ -80,6 +80,7 @@
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                   (3U)
 
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                (0x03)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                   (1)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                       (1)
 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM           (1U)
@@ -269,9 +270,9 @@
 
 #define BSP_FEATURE_SDRAM_START_ADDRESS                   (0x0U)
 
-#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE                (0) // Feature not available on this MCU
-#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN           (0) // Feature not available on this MCU
-#define BSP_FEATURE_SLCDC_MAX_NUM_SEG                     (0) // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE                (0)  // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN           (0)  // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_MAX_NUM_SEG                     (0)  // Feature not available on this MCU
 
 #define BSP_FEATURE_SPI_CLK                               (FSP_PRIV_CLOCK_PCLKA)
 #define BSP_FEATURE_SPI_HAS_BYTE_SWAP                     (1U)

diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h
@@ -80,6 +80,7 @@
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                   (3U)
 
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                (0x03)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                   (1)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                       (1)
 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM           (1U)
@@ -269,9 +270,9 @@
 
 #define BSP_FEATURE_SDRAM_START_ADDRESS                   (0x90000000U)
 
-#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE                (0) // Feature not available on this MCU
-#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN           (0) // Feature not available on this MCU
-#define BSP_FEATURE_SLCDC_MAX_NUM_SEG                     (0) // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE                (0)  // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN           (0)  // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_MAX_NUM_SEG                     (0)  // Feature not available on this MCU
 
 #define BSP_FEATURE_SPI_CLK                               (FSP_PRIV_CLOCK_PCLKA)
 #define BSP_FEATURE_SPI_HAS_BYTE_SWAP                     (1U)

diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
@@ -80,6 +80,7 @@
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                   (3U)
 
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                (0x03)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                   (1)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                       (1)
 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM           (1U)
@@ -269,9 +270,9 @@
 
 #define BSP_FEATURE_SDRAM_START_ADDRESS                   (0x90000000U)
 
-#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE                (0) // Feature not available on this MCU
-#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN           (0) // Feature not available on this MCU
-#define BSP_FEATURE_SLCDC_MAX_NUM_SEG                     (0) // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE                (0)  // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN           (0)  // Feature not available on this MCU
+#define BSP_FEATURE_SLCDC_MAX_NUM_SEG                     (0)  // Feature not available on this MCU
 
 #define BSP_FEATURE_SPI_CLK                               (FSP_PRIV_CLOCK_PCLKA)
 #define BSP_FEATURE_SPI_HAS_BYTE_SWAP                     (1U)

diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h
@@ -62,6 +62,7 @@
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                   (3U)
 
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                (0x3F)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                   (5)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                       (1)
 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM           (0U)

diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h
@@ -80,6 +80,7 @@
 #define BSP_FEATURE_ADC_VALID_UNIT_MASK                   (3U)
 
 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK                (0x03)
+#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM                   (1)
 
 #define BSP_FEATURE_BSP_FLASH_CACHE                       (1)
 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM           (1U)

diff --git a/ra/fsp/src/r_agt/r_agt.c b/ra/fsp/src/r_agt/r_agt.c
@@ -93,9 +93,9 @@ static const fsp_version_t s_agt_version =
     .code_version_major = AGT_CODE_VERSION_MAJOR,
 };
 
-/* The period for channel 0 must be known to calculate the frequency of channel 1 if the count source is AGT0
+/* The period for even channels must be known to calculate the frequency of odd channels if the count source is AGT
  * underflow. */
-static uint32_t gp_prv_agt_periods[2];
+static uint32_t gp_prv_agt_periods[BSP_FEATURE_AGT_MAX_CHANNEL_NUM + 1];
 
 /***********************************************************************************************************************
  * Global Variables
@@ -443,10 +443,12 @@ fsp_err_t R_AGT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_inf
 
     /* Get and store clock frequency */
     agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend;
-    if (AGT_CLOCK_AGT0_UNDERFLOW == p_extend->count_source)
+    if (AGT_CLOCK_AGT_UNDERFLOW == p_extend->count_source)
     {
-        /* Clock frequency is the AGT0 clock frequency divided by the period of AGT0. */
-        p_info->clock_frequency = r_agt_clock_frequency_get(R_AGT0) / gp_prv_agt_periods[0];
+        /* Clock frequency of this channel is the clock frequency divided by the timer period of the source channel. */
+        R_AGT0_Type * p_source_channel_reg = p_instance_ctrl->p_reg - (R_AGT1 - R_AGT0);
+        p_info->clock_frequency = r_agt_clock_frequency_get(p_source_channel_reg) /
+                                  gp_prv_agt_periods[p_instance_ctrl->p_cfg->channel - 1];
     }
     else
     {
@@ -641,9 +643,9 @@ static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctr
     /* Validate channel number. */
     FSP_ERROR_RETURN(((1U << p_cfg->channel) & BSP_FEATURE_AGT_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
 
-    /* AGT_CLOCK_AGT0_UNDERFLOW is not allowed on AGT channel 0. */
+    /* AGT_CLOCK_AGT_UNDERFLOW is not allowed on even AGT channels. */
     agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend;
-    FSP_ASSERT((AGT_CLOCK_AGT0_UNDERFLOW != p_extend->count_source) || (1U == p_cfg->channel));
+    FSP_ASSERT((AGT_CLOCK_AGT_UNDERFLOW != p_extend->count_source) || (p_cfg->channel & 1U));
 
     /* Validate divider. */
     if (AGT_CLOCK_PCLKB == p_extend->count_source)
@@ -652,7 +654,7 @@ static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctr
         FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_8);
         FSP_ASSERT(p_cfg->source_div != TIMER_SOURCE_DIV_4);
     }
-    else if (AGT_CLOCK_AGT0_UNDERFLOW == p_extend->count_source)
+    else if (AGT_CLOCK_AGT_UNDERFLOW == p_extend->count_source)
     {
         /* Divider not used if AGT0 underflow is selected as count source. */
         FSP_ASSERT(p_cfg->source_div == TIMER_SOURCE_DIV_1);
@@ -733,14 +735,14 @@ static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, tim
         p_instance_ctrl->p_reg->AGTIOSEL = (uint8_t) (p_extend->count_source & (uint8_t) ~AGT_CLOCK_AGTIO);
     }
 #endif
-    else if (AGT_CLOCK_AGT0_UNDERFLOW != p_extend->count_source)
+    else if (AGT_CLOCK_AGT_UNDERFLOW != p_extend->count_source)
     {
         /* Update the divider for LOCO/subclock. */
         agtmr2 = p_cfg->source_div;
     }
     else
     {
-        /* No divider can be used when count source is AGT_CLOCK_AGT0_UNDERFLOW. */
+        /* No divider can be used when count source is AGT_CLOCK_AGT_UNDERFLOW. */
     }
 
     uint32_t agtmr1 = (count_source_int | edge) | mode;

diff --git a/ra/fsp/src/rm_psa_crypto/ecdh_alt.c b/ra/fsp/src/rm_psa_crypto/ecdh_alt.c
@@ -555,6 +555,9 @@ static int ecdh_make_public_internal( mbedtls_ecdh_context_mbed *ctx,
                                              f_rng, p_rng, rs_ctx ) ) != 0 )
         return( ret );
 #else
+#if BSP_FEATURE_CRYPTO_HAS_SCE9
+    ctx->grp.vendor_ctx = (void *) true;
+#endif
     if( ( ret = mbedtls_ecdh_gen_public( &ctx->grp, &ctx->d, &ctx->Q,
                                          f_rng, p_rng ) ) != 0 )
         return( ret );