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Before testing the SMP, you need to recompile Linux kernel. Please substitude the configuration file in `configs/linux.config` to Linux source code with .config file name, and cross compile it.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,140 @@ | ||
| /dts-v1/; | ||
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| / { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| model = "semu"; | ||
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| aliases { | ||
| serial0 = "/soc@F0000000/serial@4000000"; | ||
| }; | ||
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| chosen { | ||
| bootargs = "earlycon console=ttyS0"; | ||
| stdout-path = "serial0"; | ||
| linux,initrd-start = <0x1f700000>; /* @403 MiB (503 * 1024 * 1024) */ | ||
| linux,initrd-end = <0x1fefffff>; /* @511 MiB (511 * 1024 * 1024 - 1) */ | ||
| }; | ||
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| cpus { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| timebase-frequency = <65000000>; | ||
| cpu0: cpu@0 { | ||
| status = "okay"; | ||
| device_type = "cpu"; | ||
| compatible = "riscv"; | ||
| reg = <0>; | ||
| riscv,isa = "rv32ima"; | ||
| mmu-type = "riscv,rv32"; | ||
| cpu0_intc: interrupt-controller { | ||
| #interrupt-cells = <1>; | ||
| #address-cells = <0>; | ||
| interrupt-controller; | ||
| compatible = "riscv,cpu-intc"; | ||
| }; | ||
| }; | ||
| cpu1: cpu@1 { | ||
| status = "okay"; | ||
| device_type = "cpu"; | ||
| compatible = "riscv"; | ||
| reg = <1>; | ||
| riscv,isa = "rv32ima"; | ||
| mmu-type = "riscv,rv32"; | ||
| cpu1_intc: interrupt-controller { | ||
| #interrupt-cells = <1>; | ||
| #address-cells = <0>; | ||
| interrupt-controller; | ||
| compatible = "riscv,cpu-intc"; | ||
| }; | ||
| }; | ||
| cpu2: cpu@2 { | ||
| status = "okay"; | ||
| device_type = "cpu"; | ||
| compatible = "riscv"; | ||
| reg = <2>; | ||
| riscv,isa = "rv32ima"; | ||
| mmu-type = "riscv,rv32"; | ||
| cpu2_intc: interrupt-controller { | ||
| #interrupt-cells = <1>; | ||
| #address-cells = <0>; | ||
| interrupt-controller; | ||
| compatible = "riscv,cpu-intc"; | ||
| }; | ||
| }; | ||
| cpu3: cpu@3 { | ||
| status = "okay"; | ||
| device_type = "cpu"; | ||
| compatible = "riscv"; | ||
| reg = <3>; | ||
| riscv,isa = "rv32ima"; | ||
| mmu-type = "riscv,rv32"; | ||
| cpu3_intc: interrupt-controller { | ||
| #interrupt-cells = <1>; | ||
| #address-cells = <0>; | ||
| interrupt-controller; | ||
| compatible = "riscv,cpu-intc"; | ||
| }; | ||
| }; | ||
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| }; | ||
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| sram: memory@0 { | ||
| device_type = "memory"; | ||
| reg = <0x00000000 0x20000000>; | ||
| reg-names = "sram0"; | ||
| }; | ||
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| soc: soc@F0000000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| compatible = "simple-bus"; | ||
| ranges = <0x0 0xF0000000 0x10000000>; | ||
| interrupt-parent = <&plic0>; | ||
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| plic0: interrupt-controller@0 { | ||
| #interrupt-cells = <1>; | ||
| #address-cells = <0>; | ||
| compatible = "sifive,plic-1.0.0"; | ||
| reg = <0x0000000 0x4000000>; | ||
| interrupt-controller; | ||
| interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, <&cpu2_intc 9>, <&cpu3_intc 9>; | ||
| riscv,ndev = <31>; | ||
| }; | ||
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| serial@4000000 { | ||
| compatible = "ns16550"; | ||
| reg = <0x4000000 0x100000>; | ||
| interrupts = <1>; | ||
| no-loopback-test; | ||
| clock-frequency = <5000000>; /* the baudrate divisor is ignored */ | ||
| }; | ||
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| #if SEMU_FEATURE_VIRTIONET | ||
| net0: virtio@4100000 { | ||
| compatible = "virtio,mmio"; | ||
| reg = <0x4100000 0x100000>; | ||
| interrupts = <2>; | ||
| }; | ||
| #endif | ||
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| #if SEMU_FEATURE_VIRTIOBLK | ||
| blk0: virtio@4200000 { | ||
| compatible = "virtio,mmio"; | ||
| reg = <0x4200000 0x200>; | ||
| interrupts = <3>; | ||
| }; | ||
| #endif | ||
| clint0: clint@4300000 { | ||
| compatible = "riscv,clint0"; | ||
| interrupt-controller; | ||
| interrupts-extended = | ||
| <&cpu0_intc 3 &cpu0_intc 7>, | ||
| <&cpu1_intc 3 &cpu1_intc 7>, | ||
| <&cpu2_intc 3 &cpu2_intc 7>, | ||
| <&cpu3_intc 3 &cpu3_intc 7>; | ||
| reg = <0x4300000 0x10000>; | ||
| }; | ||
| }; | ||
|
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| }; |
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