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Enable SMP by make check SMP=1
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Before testing the SMP, you need to recompile Linux kernel.
Please substitude the configuration file in `configs/linux.config`
to Linux source code with .config file name, and cross compile it.
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ranvd committed Jun 24, 2024
1 parent 6f8ba99 commit b270e76
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Showing 9 changed files with 201 additions and 100 deletions.
16 changes: 12 additions & 4 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -74,19 +74,27 @@ minimal.dtb: minimal.dts
$(subst ^,$S,$(filter -D^SEMU_FEATURE_%, $(subst -D$(S)SEMU_FEATURE,-D^SEMU_FEATURE,$(CFLAGS)))) $< \
| $(DTC) - > $@

minimal-quad.dtb: minimal-quad.dts
$(VECHO) " DTC\t$@\n"
$(Q)$(CC) -nostdinc -E -P -x assembler-with-cpp -undef \
$(subst ^,$S,$(filter -D^SEMU_FEATURE_%, $(subst -D$(S)SEMU_FEATURE,-D^SEMU_FEATURE,$(CFLAGS)))) $< \
| $(DTC) - > $@

# Rules for downloading prebuilt Linux kernel image
include mk/external.mk

ext4.img:
$(Q)dd if=/dev/zero of=$@ bs=4k count=600
$(Q)$(MKFS_EXT4) -F $@

check: $(BIN) minimal.dtb $(KERNEL_DATA) $(INITRD_DATA) $(DISKIMG_FILE)
SMP ?= 0
check: $(BIN) minimal.dtb minimal-quad.dtb $(KERNEL_DATA) $(INITRD_DATA) $(DISKIMG_FILE)
@$(call notice, Ready to launch Linux kernel. Please be patient.)
ifeq ($(SMP),1)
$(Q)./$(BIN) -k $(KERNEL_DATA) -b minimal-quad.dtb -i $(INITRD_DATA) $(OPTS)
else
$(Q)./$(BIN) -k $(KERNEL_DATA) -b minimal.dtb -i $(INITRD_DATA) $(OPTS)

debug: $(BIN) minimal.dtb $(KERNEL_DATA) $(INITRD_DATA) $(DISKIMG_FILE)
$(Q)gdb --args ./$(BIN) -k $(KERNEL_DATA) -b minimal.dtb -i $(INITRD_DATA) $(OPTS)
endif

build-image:
scripts/build-image.sh
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2 changes: 1 addition & 1 deletion configs/linux.config
Original file line number Diff line number Diff line change
Expand Up @@ -223,7 +223,7 @@ CONFIG_ARCH_RV32I=y
# CONFIG_CMODEL_MEDLOW is not set
CONFIG_CMODEL_MEDANY=y
CONFIG_MODULE_SECTIONS=y
# CONFIG_SMP is not set
CONFIG_SMP=y
CONFIG_TUNE_GENERIC=y
# CONFIG_RISCV_ISA_C is not set
CONFIG_TOOLCHAIN_HAS_ZICBOM=y
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2 changes: 1 addition & 1 deletion main.c
Original file line number Diff line number Diff line change
Expand Up @@ -505,7 +505,7 @@ static void handle_options(int argc,
hart->mem_page_table = mem_page_table; \
hart->s_mode = true; \
hart->hsm_status = SBI_HSM_STATE_STOPPED; \
hart_init(hart); \
hart_init(hart); \
})

static int semu_start(int argc, char **argv)
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140 changes: 140 additions & 0 deletions minimal-quad.dts
Original file line number Diff line number Diff line change
@@ -0,0 +1,140 @@
/dts-v1/;

/ {
#address-cells = <1>;
#size-cells = <1>;
model = "semu";

aliases {
serial0 = "/soc@F0000000/serial@4000000";
};

chosen {
bootargs = "earlycon console=ttyS0";
stdout-path = "serial0";
linux,initrd-start = <0x1f700000>; /* @403 MiB (503 * 1024 * 1024) */
linux,initrd-end = <0x1fefffff>; /* @511 MiB (511 * 1024 * 1024 - 1) */
};

cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <65000000>;
cpu0: cpu@0 {
status = "okay";
device_type = "cpu";
compatible = "riscv";
reg = <0>;
riscv,isa = "rv32ima";
mmu-type = "riscv,rv32";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
#address-cells = <0>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
cpu1: cpu@1 {
status = "okay";
device_type = "cpu";
compatible = "riscv";
reg = <1>;
riscv,isa = "rv32ima";
mmu-type = "riscv,rv32";
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
#address-cells = <0>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
cpu2: cpu@2 {
status = "okay";
device_type = "cpu";
compatible = "riscv";
reg = <2>;
riscv,isa = "rv32ima";
mmu-type = "riscv,rv32";
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
#address-cells = <0>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
cpu3: cpu@3 {
status = "okay";
device_type = "cpu";
compatible = "riscv";
reg = <3>;
riscv,isa = "rv32ima";
mmu-type = "riscv,rv32";
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
#address-cells = <0>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};

};

sram: memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>;
reg-names = "sram0";
};

soc: soc@F0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0xF0000000 0x10000000>;
interrupt-parent = <&plic0>;

plic0: interrupt-controller@0 {
#interrupt-cells = <1>;
#address-cells = <0>;
compatible = "sifive,plic-1.0.0";
reg = <0x0000000 0x4000000>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, <&cpu2_intc 9>, <&cpu3_intc 9>;
riscv,ndev = <31>;
};

serial@4000000 {
compatible = "ns16550";
reg = <0x4000000 0x100000>;
interrupts = <1>;
no-loopback-test;
clock-frequency = <5000000>; /* the baudrate divisor is ignored */
};

#if SEMU_FEATURE_VIRTIONET
net0: virtio@4100000 {
compatible = "virtio,mmio";
reg = <0x4100000 0x100000>;
interrupts = <2>;
};
#endif

#if SEMU_FEATURE_VIRTIOBLK
blk0: virtio@4200000 {
compatible = "virtio,mmio";
reg = <0x4200000 0x200>;
interrupts = <3>;
};
#endif
clint0: clint@4300000 {
compatible = "riscv,clint0";
interrupt-controller;
interrupts-extended =
<&cpu0_intc 3 &cpu0_intc 7>,
<&cpu1_intc 3 &cpu1_intc 7>,
<&cpu2_intc 3 &cpu2_intc 7>,
<&cpu3_intc 3 &cpu3_intc 7>;
reg = <0x4300000 0x10000>;
};
};

};
60 changes: 2 additions & 58 deletions minimal.dts
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,6 @@
#size-cells = <0>;
timebase-frequency = <65000000>;
cpu0: cpu@0 {
status = "okay";
device_type = "cpu";
compatible = "riscv";
reg = <0>;
Expand All @@ -34,49 +33,6 @@
compatible = "riscv,cpu-intc";
};
};
cpu1: cpu@1 {
status = "okay";
device_type = "cpu";
compatible = "riscv";
reg = <1>;
riscv,isa = "rv32ima";
mmu-type = "riscv,rv32";
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
#address-cells = <0>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
cpu2: cpu@2 {
status = "okay";
device_type = "cpu";
compatible = "riscv";
reg = <2>;
riscv,isa = "rv32ima";
mmu-type = "riscv,rv32";
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
#address-cells = <0>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
cpu3: cpu@3 {
status = "okay";
device_type = "cpu";
compatible = "riscv";
reg = <3>;
riscv,isa = "rv32ima";
mmu-type = "riscv,rv32";
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
#address-cells = <0>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};

};

sram: memory@0 {
Expand All @@ -98,8 +54,7 @@
compatible = "sifive,plic-1.0.0";
reg = <0x0000000 0x4000000>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, <&cpu2_intc 9>, <&cpu3_intc 9>;
// interrupts-extended = <&cpu0_intc 9 &cpu0_intc 11>, <&cpu1_intc 9 &cpu1_intc 11>, <&cpu2_intc 9 &cpu2_intc 11>, <&cpu3_intc 9 &cpu3_intc 11>;
interrupts-extended = <&cpu0_intc 9>;
riscv,ndev = <31>;
};

Expand All @@ -126,16 +81,5 @@
interrupts = <3>;
};
#endif
clint0: clint@4300000 {
compatible = "riscv,clint0";
interrupt-controller;
interrupts-extended =
<&cpu0_intc 3 &cpu0_intc 7>,
<&cpu1_intc 3 &cpu1_intc 7>,
<&cpu2_intc 3 &cpu2_intc 7>,
<&cpu3_intc 3 &cpu3_intc 7>;
reg = <0x4300000 0x10000>;
};
};

};
};
13 changes: 6 additions & 7 deletions plic.c
Original file line number Diff line number Diff line change
Expand Up @@ -11,12 +11,11 @@ void plic_update_interrupts(vm_t *vm, plic_state_t *plic)
plic->ip |= plic->active & ~plic->masked;
plic->masked |= plic->active;
/* Send interrupt to target */
for (uint32_t i = 0; i < vm->hart_number; i++){

if (plic->ip & plic->ie[i])
vm->hart[i]->sip |= RV_INT_SEI_BIT;
else
vm->hart[i]->sip &= ~RV_INT_SEI_BIT;
for (uint32_t i = 0; i < vm->hart_number; i++) {
if (plic->ip & plic->ie[i])
vm->hart[i]->sip |= RV_INT_SEI_BIT;
else
vm->hart[i]->sip &= ~RV_INT_SEI_BIT;
}
}

Expand All @@ -26,7 +25,7 @@ static bool plic_reg_read(plic_state_t *plic, uint32_t addr, uint32_t *value)
if (1 <= addr && addr <= 31)
return true;

if (addr == 0x400){
if (addr == 0x400) {
*value = plic->ip;
return true;
}
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16 changes: 8 additions & 8 deletions ram.c
Original file line number Diff line number Diff line change
Expand Up @@ -2,15 +2,15 @@
#include "riscv_private.h"

/* RAM handlers (address must be relative, assumes it is within bounds) */
#define RAM_FUNC(width, code) \
do { \
if (unlikely((addr & (width - 1)))) { \
#define RAM_FUNC(width, code) \
do { \
if (unlikely((addr & (width - 1)))) { \
hart_set_exception(hart, exc_cause, hart->exc_val); \
break; \
} \
UNUSED uint8_t offset = (addr & 0b11) * 8; \
uint32_t *cell = &mem[addr >> 2]; \
code; \
break; \
} \
UNUSED uint8_t offset = (addr & 0b11) * 8; \
uint32_t *cell = &mem[addr >> 2]; \
code; \
} while (0)

void ram_read(hart_t *hart,
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