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Restrict controlled from non-thru registers #1305
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516547e
Restrict controlled from non-thru registers
mpharrigan c5f301b
lint
mpharrigan 2e2e6e5
Merge branch 'main' into 2024-08/non-thru-ctrl
mpharrigan 05d6c5e
format
mpharrigan 816b4f4
Merge remote-tracking branch 'origin/main' into 2024-08/non-thru-ctrl
mpharrigan 8b08a5e
Merge branch 'main' into 2024-08/non-thru-ctrl
mpharrigan ecf2b25
Merge branch 'main' into 2024-08/non-thru-ctrl
mpharrigan 32b10fa
Merge branch 'main' into 2024-08/non-thru-ctrl
mpharrigan bca3a11
Move error condition to usages
mpharrigan bcda6f3
Merge branch 'main' into 2024-08/non-thru-ctrl
mpharrigan 5f5defc
Merge branch 'main' into 2024-08/non-thru-ctrl
mpharrigan 33c8d54
Merge branch 'main' into 2024-08/non-thru-ctrl
mpharrigan 7c574e6
Merge branch 'main' into 2024-08/non-thru-ctrl
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Original file line number | Diff line number | Diff line change |
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@@ -11,51 +11,32 @@ | |
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
# See the License for the specific language governing permissions and | ||
# limitations under the License. | ||
from typing import Dict, List, Tuple, TYPE_CHECKING | ||
from typing import List, TYPE_CHECKING | ||
|
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import attrs | ||
import cirq | ||
import numpy as np | ||
import pytest | ||
|
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import qualtran.testing as qlt_testing | ||
from qualtran import ( | ||
Bloq, | ||
BloqBuilder, | ||
CompositeBloq, | ||
Controlled, | ||
CtrlSpec, | ||
QBit, | ||
QInt, | ||
QUInt, | ||
Register, | ||
Side, | ||
Signature, | ||
) | ||
from qualtran import Bloq, CompositeBloq, Controlled, CtrlSpec, QBit, QInt, QUInt | ||
from qualtran._infra.gate_with_registers import get_named_qubits, merge_qubits | ||
from qualtran.bloqs.basic_gates import ( | ||
CSwap, | ||
GlobalPhase, | ||
IntEffect, | ||
IntState, | ||
OneState, | ||
Swap, | ||
TwoBitCSwap, | ||
XGate, | ||
XPowGate, | ||
YGate, | ||
ZeroState, | ||
ZGate, | ||
) | ||
from qualtran.bloqs.for_testing import TestAtom, TestParallelCombo, TestSerialCombo | ||
from qualtran.bloqs.mcmt import And | ||
from qualtran.cirq_interop.testing import GateHelper | ||
from qualtran.drawing import get_musical_score_data | ||
from qualtran.drawing.musical_score import Circle, SoqData, TextBox | ||
from qualtran.simulation.tensor import cbloq_to_quimb, get_right_and_left_inds | ||
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if TYPE_CHECKING: | ||
from qualtran import SoquetT | ||
pass | ||
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def test_ctrl_spec(): | ||
|
@@ -385,62 +366,6 @@ def test_controlled_global_phase_tensor(): | |
np.testing.assert_allclose(bloq.tensor_contract(), should_be) | ||
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@attrs.frozen | ||
class TestCtrlStatePrepAnd(Bloq): | ||
"""Decomposes into a Controlled-AND gate + int effects & targets where ctrl is active. | ||
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Tensor contraction should give the output state vector corresponding to applying an | ||
`And(and_ctrl)`; assuming all the control bits are active. | ||
""" | ||
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ctrl_spec: CtrlSpec | ||
and_ctrl: Tuple[int, int] | ||
Comment on lines
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Can we add a private flag to the |
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@property | ||
def signature(self) -> 'Signature': | ||
return Signature([Register('x', QBit(), shape=(3,), side=Side.RIGHT)]) | ||
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def build_composite_bloq(self, bb: 'BloqBuilder') -> Dict[str, 'SoquetT']: | ||
one_or_zero = [ZeroState(), OneState()] | ||
ctrl_bloq = Controlled(And(*self.and_ctrl), ctrl_spec=self.ctrl_spec) | ||
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ctrl_soqs = {} | ||
for reg, cvs in zip(ctrl_bloq.ctrl_regs, self.ctrl_spec.cvs): | ||
soqs = np.empty(shape=reg.shape, dtype=object) | ||
for idx in reg.all_idxs(): | ||
soqs[idx] = bb.add(IntState(val=cvs[idx], bitsize=reg.dtype.num_qubits)) | ||
ctrl_soqs[reg.name] = soqs | ||
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and_ctrl = [bb.add(one_or_zero[cv]) for cv in self.and_ctrl] | ||
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ctrl_soqs = bb.add_d(ctrl_bloq, **ctrl_soqs, ctrl=and_ctrl) | ||
out_soqs = np.asarray([*ctrl_soqs.pop('ctrl'), ctrl_soqs.pop('target')]) # type: ignore[misc] | ||
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for reg, cvs in zip(ctrl_bloq.ctrl_regs, self.ctrl_spec.cvs): | ||
for idx in reg.all_idxs(): | ||
ctrl_soq = np.asarray(ctrl_soqs[reg.name])[idx] | ||
bb.add(IntEffect(val=cvs[idx], bitsize=reg.dtype.num_qubits), val=ctrl_soq) | ||
return {'x': out_soqs} | ||
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def _verify_ctrl_tensor_for_and(ctrl_spec: CtrlSpec, and_ctrl: Tuple[int, int]): | ||
bloq = TestCtrlStatePrepAnd(ctrl_spec, and_ctrl) | ||
bloq_tensor = bloq.tensor_contract() | ||
cirq_state_vector = GateHelper(And(*and_ctrl)).circuit.final_state_vector( | ||
initial_state=and_ctrl + (0,) | ||
) | ||
np.testing.assert_allclose(bloq_tensor, cirq_state_vector, atol=1e-8) | ||
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@pytest.mark.parametrize('ctrl_spec', interesting_ctrl_specs) | ||
def test_controlled_tensor_for_and_bloq(ctrl_spec: CtrlSpec): | ||
# Test AND gate with one-sided signature (aka controlled state preparation). | ||
_verify_ctrl_tensor_for_and(ctrl_spec, (1, 1)) | ||
_verify_ctrl_tensor_for_and(ctrl_spec, (1, 0)) | ||
_verify_ctrl_tensor_for_and(ctrl_spec, (0, 1)) | ||
_verify_ctrl_tensor_for_and(ctrl_spec, (0, 0)) | ||
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def test_controlled_diagrams(): | ||
ctrl_gate = XPowGate(0.25).controlled() | ||
cirq.testing.assert_has_diagram( | ||
|
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See other comment -- it'll be great if we can guard this with a flag set to TRUE by default. When we relax the condition, we can get rid of the flag and also keep the tests around.