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Merge branch 'main' into 2024/11/10-fix-qpe-sim-tests
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anurudhp authored Nov 12, 2024
2 parents 30ab20b + 2c2a3aa commit d2d22e2
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120 changes: 49 additions & 71 deletions qualtran/bloqs/arithmetic/addition.ipynb
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"cells": [
{
"cell_type": "markdown",
"id": "c231998b",
"id": "c9483021",
"metadata": {
"cq.autogen": "title_cell"
},
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{
"cell_type": "code",
"execution_count": null,
"id": "b572d769",
"id": "2dd760e6",
"metadata": {
"cq.autogen": "top_imports"
},
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},
{
"cell_type": "markdown",
"id": "d3f4ce95",
"id": "95d8998c",
"metadata": {
"cq.autogen": "Add.bloq_doc.md"
},
Expand All @@ -55,7 +55,7 @@
{
"cell_type": "code",
"execution_count": null,
"id": "6426bb53",
"id": "4cb5b704",
"metadata": {
"cq.autogen": "Add.bloq_doc.py"
},
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},
{
"cell_type": "markdown",
"id": "3c8caad1",
"id": "69f415a2",
"metadata": {
"cq.autogen": "Add.example_instances.md"
},
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{
"cell_type": "code",
"execution_count": null,
"id": "73929b65",
"id": "b0c9815d",
"metadata": {
"cq.autogen": "Add.add_small"
"cq.autogen": "Add.add_symb"
},
"outputs": [],
"source": [
"add_small = Add(QUInt(bitsize=4))"
"n = sympy.Symbol('n')\n",
"add_symb = Add(QInt(bitsize=n))"
]
},
{
"cell_type": "code",
"execution_count": null,
"id": "fbd4dbe9",
"id": "b481bd7d",
"metadata": {
"cq.autogen": "Add.add_large"
"cq.autogen": "Add.add_small"
},
"outputs": [],
"source": [
"add_large = Add(QUInt(bitsize=64))"
"add_small = Add(QUInt(bitsize=4))"
]
},
{
"cell_type": "code",
"execution_count": null,
"id": "e749abdb",
"id": "90bc9e29",
"metadata": {
"cq.autogen": "Add.add_symb"
"cq.autogen": "Add.add_large"
},
"outputs": [],
"source": [
"n = sympy.Symbol('n')\n",
"add_symb = Add(QInt(bitsize=n))"
"add_large = Add(QUInt(bitsize=64))"
]
},
{
"cell_type": "code",
"execution_count": null,
"id": "e5b746c1",
"id": "2fbbb318",
"metadata": {
"collapsed": false
"cq.autogen": "Add.add_diff_size_regs"
},
"outputs": [],
"source": [
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},
{
"cell_type": "markdown",
"id": "c3c1a7e4",
"id": "253212ec",
"metadata": {
"cq.autogen": "Add.graphical_signature.md"
},
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{
"cell_type": "code",
"execution_count": null,
"id": "0f92be09",
"id": "ed24479f",
"metadata": {
"cq.autogen": "Add.graphical_signature.py"
},
Expand All @@ -149,7 +149,7 @@
},
{
"cell_type": "markdown",
"id": "350cb374",
"id": "1c55412d",
"metadata": {
"cq.autogen": "Add.call_graph.md"
},
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{
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"id": "c36a3fc4",
"id": "90569a0c",
"metadata": {
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},
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},
{
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"id": "ffc76cc5",
"id": "8ae20541",
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"cq.autogen": "OutOfPlaceAdder.bloq_doc.md"
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{
"cell_type": "code",
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},
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},
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},
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{
"cell_type": "code",
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"cq.autogen": "OutOfPlaceAdder.add_oop_symb"
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Expand All @@ -237,7 +237,7 @@
{
"cell_type": "code",
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{
"cell_type": "code",
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Expand All @@ -260,7 +260,7 @@
},
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"cq.autogen": "OutOfPlaceAdder.graphical_signature.md"
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{
"cell_type": "code",
"execution_count": null,
"id": "d117e345",
"id": "672073d0",
"metadata": {
"cq.autogen": "OutOfPlaceAdder.graphical_signature.py"
},
Expand All @@ -284,7 +284,7 @@
},
{
"cell_type": "markdown",
"id": "3b6469e0",
"id": "ab488ede",
"metadata": {
"cq.autogen": "OutOfPlaceAdder.call_graph.md"
},
Expand All @@ -295,7 +295,7 @@
{
"cell_type": "code",
"execution_count": null,
"id": "ff84301f",
"id": "311c752e",
"metadata": {
"cq.autogen": "OutOfPlaceAdder.call_graph.py"
},
Expand All @@ -309,7 +309,7 @@
},
{
"cell_type": "markdown",
"id": "2813f173",
"id": "62b014b7",
"metadata": {
"cq.autogen": "AddK.bloq_doc.md"
},
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"only clifford operations.\n",
"\n",
"#### Parameters\n",
" - `bitsize`: Number of bits used to represent each integer.\n",
" - `dtype`: data type of the input register `x`\n",
" - `k`: The classical integer value to be added to x.\n",
" - `cvs`: A tuple of control values. Each entry specifies whether that control line is a \"positive\" control (`cv[i]=1`) or a \"negative\" control (`cv[i]=0`).\n",
" - `signed`: A boolean condition which controls whether the x register holds a value represented in 2's Complement or Unsigned. This affects the ability to add a negative constant. \n",
" - `is_controlled`: if True, construct a singly-controlled bloq. \n",
"\n",
"#### Registers\n",
" - `x`: A bitsize-sized input register (register x above). \n",
" - `x`: register of type `self.dtype` \n",
"\n",
"#### References\n",
" - [Improved quantum circuits for elliptic curve discrete logarithms](https://arxiv.org/abs/2001.09580). Haner et al. 2020. Section 3: Components. \"Integer addition\" and Fig 2a.\n"
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{
"cell_type": "code",
"execution_count": null,
"id": "cd255bf9",
"id": "3155864a",
"metadata": {
"cq.autogen": "AddK.bloq_doc.py"
},
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},
{
"cell_type": "markdown",
"id": "7538f9a5",
"id": "9009b701",
"metadata": {
"cq.autogen": "AddK.example_instances.md"
},
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{
"cell_type": "code",
"execution_count": null,
"id": "4305289f",
"id": "7e2a9fdf",
"metadata": {
"cq.autogen": "AddK.add_k"
},
"outputs": [],
"source": [
"n, k = sympy.symbols('n k')\n",
"add_k = AddK(bitsize=n, k=k)"
"add_k = AddK(QUInt(n), k=k)"
]
},
{
"cell_type": "code",
"execution_count": null,
"id": "f6048819",
"id": "f4e218da",
"metadata": {
"cq.autogen": "AddK.add_k_small"
},
"outputs": [],
"source": [
"add_k_small = AddK(bitsize=4, k=2, signed=False)"
"add_k_small = AddK(QUInt(4), k=2)"
]
},
{
"cell_type": "code",
"execution_count": null,
"id": "b67fd469",
"id": "97073a76",
"metadata": {
"cq.autogen": "AddK.add_k_large"
},
"outputs": [],
"source": [
"add_k_large = AddK(bitsize=64, k=-23, signed=True)"
"add_k_large = AddK(QInt(64), k=-23)"
]
},
{
"cell_type": "markdown",
"id": "b8b04228",
"id": "57f1032d",
"metadata": {
"cq.autogen": "AddK.graphical_signature.md"
},
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{
"cell_type": "code",
"execution_count": null,
"id": "e93e7f2e",
"id": "d5d7dad4",
"metadata": {
"cq.autogen": "AddK.graphical_signature.py"
},
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},
{
"cell_type": "markdown",
"id": "13552795",
"id": "f1a51ffb",
"metadata": {
"cq.autogen": "AddK.call_graph.md"
},
Expand All @@ -432,7 +431,7 @@
{
"cell_type": "code",
"execution_count": null,
"id": "d8d6584e",
"id": "cbfc2d39",
"metadata": {
"cq.autogen": "AddK.call_graph.py"
},
Expand All @@ -443,37 +442,16 @@
"show_call_graph(add_k_g)\n",
"show_counts_sigma(add_k_sigma)"
]
},
{
"cell_type": "code",
"execution_count": null,
"id": "8853ae5d",
"metadata": {
"cq.autogen": "Add.add_diff_size_regs"
},
"outputs": [],
"source": [
"add_diff_size_regs = Add(QUInt(bitsize=4), QUInt(bitsize=16))"
]
}
],
"metadata": {
"kernelspec": {
"display_name": "Python 3 (ipykernel)",
"display_name": "Python 3",
"language": "python",
"name": "python3"
},
"language_info": {
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"name": "ipython",
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"file_extension": ".py",
"mimetype": "text/x-python",
"name": "python",
"nbconvert_exporter": "python",
"pygments_lexer": "ipython3",
"version": "3.11.7"
"name": "python"
}
},
"nbformat": 4,
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