Add RISC-V V Support #2
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The issue was that when compiling u-boot from the cva6-sdk for Cheshire + Ara we used a newer compiler (GCC 13.2.0). This compiler complies with a newer version of the RISC-V specifications, where some instruction where removed from the base integer instruction set and moved into dedicated extensions (zicsr and zifence). In the cva6-sdk, when we compile for Cheshire + Ara, the RVV variable has to be defined, for this reason we check here if this variable is defined an change the march accordingly Signed-off-by: Moritz Imfeld <[email protected]>
Signed-off-by: Moritz Imfeld <[email protected]>
Signed-off-by: Moritz Imfeld <[email protected]>
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