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Rework alloc_module_interface to reuse initialize_interface code and …
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…initial stages of Latency annotations
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VonTum committed Jan 10, 2024
1 parent c64e01f commit 8fe2407
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Showing 11 changed files with 136 additions and 123 deletions.
5 changes: 5 additions & 0 deletions README.md
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Expand Up @@ -33,6 +33,7 @@ The main goals of the language are roughly listed below:
- [ ] Arbitrary FPGA hardware full flow
- [x] Generative Code
- [ ] Templates

### Parsing
- [x] Basic Tokenizer
- [x] Basic Syntax Error Reporting
Expand All @@ -45,6 +46,8 @@ The main goals of the language are roughly listed below:
- [x] Can Parse Multiply-Add pipeline
- [x] Can Parse Blur2 filter
- [x] If Statements
- [x] Latency Specifiers
- [ ] Bound Specifiers
- [ ] Structs
- [x] For Loops
- [ ] Multi-Interface Syntax
Expand All @@ -71,6 +74,8 @@ The main goals of the language are roughly listed below:
- [x] Basic LSP for VSCode integration
- [x] Syntax Highlighting
- [x] Error and Warning Reporting
- [ ] Hover type information
- [ ] Code completion
- [ ] Per-Line Resource Utilization Reporting

### Code Generation
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5 changes: 5 additions & 0 deletions multiply_add.sus
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Expand Up @@ -360,6 +360,11 @@ module first_bit_idx_6 : bool[6] bits -> int first, bool all_zeros {

}

module multiply_add_with_latencies : int a'0, int b'0, int c'0 -> int r'0 {
int tmp'1 = multiply(a, b);
reg r = tmp + c;
}

module first_bit_idx_24 : bool[24] bits -> int first {
int[4] offsets;
bool[4] was_nonzeros;
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8 changes: 4 additions & 4 deletions src/ast.rs
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Expand Up @@ -44,8 +44,7 @@ pub enum IdentifierType {
Output,
Local,
State,
Generative,
Virtual // Generated at the interfaces of submodule instantiations
Generative
}

impl From<usize> for Span {
Expand Down Expand Up @@ -74,8 +73,9 @@ pub struct SignalDeclaration {
pub span : Span,
pub name_token : usize,
pub typ : SpanTypeExpression,
pub name : Box<str>, // File position
pub identifier_type : IdentifierType
pub name : Box<str>,
pub identifier_type : IdentifierType,
pub latency_expr : Option<SpanExpression>
}

#[derive(Debug,Clone,Copy)]
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2 changes: 1 addition & 1 deletion src/codegen_fallback.rs
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Expand Up @@ -71,7 +71,7 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> String
// Don't print named inputs and outputs, already did that in interface
match wire_decl.identifier_type {
IdentifierType::Input | IdentifierType::Output => {continue;}
IdentifierType::Local | IdentifierType::State | IdentifierType::Generative | IdentifierType::Virtual => {}
IdentifierType::Local | IdentifierType::State | IdentifierType::Generative => {}
}
}
let wire_or_reg = if let RealWireDataSource::Multiplexer{is_state: initial_value, sources: _} = &w.source {
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1 change: 0 additions & 1 deletion src/dev_aid/lsp.rs
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Expand Up @@ -135,7 +135,6 @@ fn get_semantic_token_type_from_ide_token(tok : &IDEToken) -> u32 {
IDETokenType::Identifier(IDEIdentifierType::Value(IdentifierType::State)) => 3,
IDETokenType::Identifier(IDEIdentifierType::Value(IdentifierType::Local)) => 3,
IDETokenType::Identifier(IDEIdentifierType::Value(IdentifierType::Generative)) => 3,
IDETokenType::Identifier(IDEIdentifierType::Value(IdentifierType::Virtual)) => unreachable!(),
IDETokenType::Identifier(IDEIdentifierType::Constant) => 9, // make it 'OPERATOR'?
IDETokenType::Identifier(IDEIdentifierType::Unknown) => 2, // make it 'OPERATOR'?
IDETokenType::Identifier(IDEIdentifierType::Interface) => 7, // FUNCTION
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10 changes: 4 additions & 6 deletions src/dev_aid/syntax_highlighting.rs
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Expand Up @@ -75,7 +75,6 @@ fn pretty_print(file_text : &str, tokens : &[Token], ide_infos : &[IDEToken]) {
IDETokenType::Identifier(IDEIdentifierType::Value(IdentifierType::Input)) => Style::new().blue().bright(),
IDETokenType::Identifier(IDEIdentifierType::Value(IdentifierType::Output)) => Style::new().blue().dim(),
IDETokenType::Identifier(IDEIdentifierType::Value(IdentifierType::Generative)) => Style::new().blue().bright().bold(),
IDETokenType::Identifier(IDEIdentifierType::Value(IdentifierType::Virtual)) => unreachable!(),
IDETokenType::Identifier(IDEIdentifierType::Constant) => Style::new().blue().bold(),
IDETokenType::Identifier(IDEIdentifierType::Type) => Style::new().magenta().bright(),
IDETokenType::Identifier(IDEIdentifierType::Interface) => Style::new().yellow(),
Expand Down Expand Up @@ -124,18 +123,17 @@ fn walk_name_color(all_objects : &[NamedUUID], links : &Links, result : &mut [ID
Instantiation::Wire(w) => {
if let &WireSource::WireRead{from_wire} = &w.source {
let decl = module.flattened.instantiations[from_wire].extract_wire_declaration();
if decl.identifier_type == IdentifierType::Virtual {continue;} // Virtual wires don't appear in the program text
if decl.is_remote_declaration.is_some() {continue;} // Virtual wires don't appear in this program text
result[w.span.assert_is_single_token()].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
}
}
Instantiation::WireDeclaration(decl) => {
if decl.identifier_type == IdentifierType::Virtual {continue;} // Virtual wires don't appear in the program text
let Some(name_token) = decl.name_token else {continue};
result[name_token].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
if decl.is_remote_declaration.is_some() {continue;} // Virtual wires don't appear in this program text
result[decl.name_token].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
}
Instantiation::Connection(conn) => {
let decl = module.flattened.instantiations[conn.to.root].extract_wire_declaration();
if decl.identifier_type == IdentifierType::Virtual {continue;} // Virtual wires don't appear in the program text
if decl.is_remote_declaration.is_some() {continue;} // Virtual wires don't appear in this program text
result[conn.to.span.0].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
}
Instantiation::SubModule(_) | Instantiation::IfStatement(_) | Instantiation::ForStatement(_) => {}
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