Perform Type Resolution separately after flatten

pc2 · Jan 4, 2024 · 8635e4e · 8635e4e
1 parent 68c915b
commit 8635e4e
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Showing 7 changed files with 217 additions and 132 deletions.
diff --git a/src/ast.rs b/src/ast.rs
@@ -2,7 +2,7 @@
 
 use crate::{tokenizer::{TokenTypeIdx, get_token_type_name}, linker::{NamedUUID, FileUUID, Linker}, flattening::{FlattenedModule, FlattenedInterface}, arena_alloc::{UUIDMarker, UUID, FlatAlloc}, instantiation::InstantiationList, value::Value};
 use core::ops::Range;
-use std::{fmt::Display, ops::Deref};
+use std::{fmt::Display, ops::Deref, cell::RefCell};
 
 // Token span. Indices are INCLUSIVE
 #[derive(Clone,Copy,Debug,PartialEq,Eq)]
@@ -146,23 +146,23 @@ pub struct Module {
     pub declarations : FlatAlloc<SignalDeclaration, DeclIDMarker>,
     pub code : CodeBlock,
 
-    pub interface : FlattenedInterface,
-    pub flattened : FlattenedModule,
+    pub flattened : RefCell<FlattenedModule>,
 
     pub instantiations : InstantiationList
 }
 
 impl Module {
     pub fn print_flattened_module(&self, linker : &Linker) {
         println!("Interface:");
-        for (port_idx, port) in self.interface.interface_wires.iter().enumerate() {
-            let port_direction = if port_idx < self.interface.outputs_start {"input"} else {"output"};
+        let flattened_borrow = self.flattened.borrow();
+        for (port_idx, port) in flattened_borrow.interface.interface_wires.iter().enumerate() {
+            let port_direction = if port_idx < flattened_borrow.interface.outputs_start {"input"} else {"output"};
             let port_type = port.typ.to_string(linker);
             let port_name = &port.port_name;
             println!("    {port_direction} {port_type} {port_name} -> {:?}", port.wire_id);
         }
         println!("Instantiations:");
-        for (id, inst) in &self.flattened.instantiations {
+        for (id, inst) in &flattened_borrow.instantiations {
             println!("    {:?}: {:?}", id, inst);
         }
     }

diff --git a/src/codegen_fallback.rs b/src/codegen_fallback.rs
@@ -56,9 +56,10 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> String
     assert!(!instance.errors.did_error(), "Module cannot have experienced an error");
     let mut program_text : String = format!("module {}(\n\tinput clk, \n", md.link_info.name);
     let submodule_interface = instance.interface.as_ref().unwrap();
-    for (port_idx, (port, real_port)) in zip(md.interface.interface_wires.iter(), submodule_interface).enumerate() {
+    let flattened_borrow = md.flattened.borrow();
+    for (port_idx, (port, real_port)) in zip(flattened_borrow.interface.interface_wires.iter(), submodule_interface).enumerate() {
         let wire = &instance.wires[*real_port];
-        program_text.push_str(if port_idx < md.interface.outputs_start {"\tinput"} else {"\toutput /*mux_wire*/ reg"});
+        program_text.push_str(if port_idx < flattened_borrow.interface.outputs_start {"\tinput"} else {"\toutput /*mux_wire*/ reg"});
         program_text.push_str(&typ_to_verilog_array(&wire.typ));
         program_text.push(' ');
         program_text.push_str(&wire.name);
@@ -67,7 +68,7 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> String
     program_text.push_str(");\n");
 
     for (_id, w) in &instance.wires {
-        if let Instantiation::WireDeclaration(wire_decl) = &md.flattened.instantiations[w.original_wire] {
+        if let Instantiation::WireDeclaration(wire_decl) = &flattened_borrow.instantiations[w.original_wire] {
             // Don't print named inputs and outputs, already did that in interface
             match wire_decl.identifier_type {
                 IdentifierType::Input | IdentifierType::Output => {continue;}